Xilinx clk to out variation

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View
If I register all my signals in the IOB and use the global clock,
why is the clock to out different on different outputs?
Why does my clock to out vary from compile to compile?

clock to out ranges 4.664ns to 5.355ns
Is this just skew in the global clock?
Can it be controlled with constraints?

I am using Synplify 7.2, XST 5.2.03, Win2K SP4, XCV1000E-6FG860C

Alan Nishioka

Re: Xilinx clk to out variation
I suspect you're seeing variations in the routing delay caused by
your internal clock having to 'jump' off its global clock lines
onto slower nets to get to the output IOB.  To avoid this, I use
a Xilinx DDR pad to drive my clock signals out of the chip.

Try something like:

// instantiate a DDR type I/O cell for low clock output skew
FDDRRSE uddr_clk(
        .Q              (sram_clk),
        .C0             (g_sr_clk),
        .C1             (~g_sr_clk),
        .CE             (1'b1),
        .D0             (1'b1),
        .D1             (1'b0),
        .R              (1'b0),
        .S              (1'b0)

This keeps the clock signal (g_sr_clk) on the dedicated clock lines thus
avoiding odd routing delays.

Good Luck!

John Providenza
Providenza & Boekelheide, Inc

snipped-for-privacy@accom.com (Alan Nishioka) wrote in message
Quoted text here. Click to load it

Site Timeline