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Xilinx Chipscope VIO Core Utilization

Dear Google Group Members,

Does anyone know how to instantiate a Xilinx Chipscope Pro VIO Core? I understand that one must use component declarations in VHDL for the VIO core, and therefore also for the ICON and ILA modules

The following is a component declaration for the ICON core when using the Xilinx Chipscope Pro Core Generator and the radio button "Enable Unused Boundary Scan Ports (Only if necessary)" is not selected.

--------------------------------------------------------------- component icon port ( control0 : out std_logic_vector(35 downto 0) ); end component;

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My question is how does Xilinx ChipScope 6.3.03i communicate with the core? There are not inputs to the core, only an output std_logic_vector bus.

When generating the ICON core, if the radio button is selected, "Enable Unused Boundary Scan Ports (Only if necessary)" in the ICON Parameters box the following component declaration is generated

------------------------------------------------------------------- component icon port ( tdo_in : in std_logic; capture_out : out std_logic; tdi_out : out std_logic; reset_out : out std_logic; shift_out : out std_logic; update_out : out std_logic; sel_out : out std_logic; drck_out : out std_logic; control0 : out std_logic_vector(35 downto 0) ); end component;

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Another question I have for the group is that how does the first component declaration communicate to the PC via JTAG/Boundary Scan if there are no input signals? Which component declaration should I choose?

Thank you responders in advance for answers to the above questions.

Reply to
happydude32905
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In order to a VIO core to your design you must also have an ICON core in your design. Connect the bidirectional control bus from the ICON core to the control bus of the VIO core to provide communication and then connect the user side inputs and outputs to wherever you need them in the design.

Here's a Verilog Example snippet with 3 VIO cores:

wire [35:0] icon_control0; wire [35:0] icon_control1; wire [35:0] icon_control2;

wire [31:0] sync0_in; wire [31:0] sync0_out;

wire [179:0] sync1_in; wire [31:0] sync1_out;

wire [31:0] sync2_in; wire [219:0] sync2_out;

// // ChipScope Integrated Controller Core (3 ports) // icon_3 i_icon ( .control0 (icon_control0), .control1 (icon_control1), .control2 (icon_control2) );

// // ChipScope VIO Core for MGT Adaptive IO controls // vio_32_32 i_vio_0 ( .control( icon_control0), .clk( usrclk_g[0]), .sync_in( sync0_in), .sync_out( sync0_out) );

// // ChipScope VIO Core for Addressable BERT controls // vio_180_32 i_vio_1 ( .control( icon_control1), .clk( usrclk_g[1]), .sync_in( sync1_in), .sync_out( sync1_out) );

// // ChipScope VIO Core for Addressable CLB & IOB Noise controls // vio_32_220 i_vio_2 ( .control( icon_control2), .clk( usrclk_g[2]), .sync_in( sync2_in), .sync_out( sync2_out) );

Both ICON questions are linked together, so I'm going to answer them as one.

The ICON (Integrated CONtroller) core includes a BSCAN primitive as part of its netlist. The BSCAN primitive can be accessed by the JTAG chain using special instructions for a USER1 and USER2 internal scan chains.

Selecting the "Enable Unused Boundary Scan Ports" allows you to bring out the other port on the BSCAN primitive so that it can be used by your own custom scan chain if you need it.

Ed

Reply to
Ed McGettigan

schrieb im Newsbeitrag news: snipped-for-privacy@g44g2000cwa.googlegroups.com...

the BSCAN primitive has internal connections to the JTAG pins, those are shown in the bscan primitive.

control0 is actually not output only vector, bit 3 is reverse direction, that causes sometimes problems in the synthesis.

using VIO is real simple, just use the icon (as above) connect the control from icon to vio, your signal to vio and that it.

Antti PS gforge.openchip.org I think there is verilog source code of 3rd party VIO output compatible core take a look if you want to know the internals

Reply to
Antti Lukats

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