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Xilinx BUFGMUX Setup Time requirement clarification needed

Hello,

e.g. the XC3SE Datasheet ds312 tells on page 59 in the Clock Buffers/Multiplexers section:

"As specified in DC and Switching Characteristics (Module 3), the select input has a setup time requirement."

This is probaly Tgsi on page 139.

What can happen if the setup time is not met ("End of the world as we knew it?:-)) ? Does the select signal need to be aligned to both input clock edges? If it needs to be aligned to both clocks, how does one achieve that. An if there are that harsh requirements on the select signal, what's the whole point in the BUFGMUX?

Or does the select signal only needs to be aligned with the active edge. Simple latching the enable signal with the BUFGMUX output clock and feeding the latch output to the select of BUFGMUX would do the job (beside the case where the active clock is slow, where the time to the next clock would be needed before the clocks would switch.

Some clarification would be fine.

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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Reply to
Uwe Bonnes
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Hello,

I compared the text in the Spartan-3E data sheet to that in the Spartan-3 data sheet. Here's what the Spartan-3 data sheet had to say:

Looks like that information somehow got dropped when the Spartan-3E data sheet was created, but you'll also notice the attempt to provide more information about where to find the parameter. You are right, it is Tgsi.

Eric

"Uwe B> e.g. the XC3SE Datasheet ds312 tells on page 59 in the Clock

Reply to
Eric Crabill

Reply to
Peter Alfke

All,

The BUFGMUX has become more complex, not less in its recent appearances on the FPGA stage.

It is a completely synchronous machine, so it does matter if the request to switch has sufficient setup time. If it does not, then it will not switch until the next clock edge.

There was a small group which wanted to place an asynchronous state machine version of the BUFGMUX in the parts (I was part of that effort). Unfortunately, that design was not chosen to be used. It had a number of advantages: can switch away from a failed clock, and had no requirement for a setup time. It was also a very trivial circuit with one control.

Alas, asynchronous circuits even when they are working perfectly in simulation still represent a huge risk as they may not work so well in silicon.

Aust> Asynchronously switching between two unrelated clock frequencies is an

Reply to
Austin Lesea

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