Hi there
i am using an old virtex FPGA. My design runs well in post place and routed functional simulation. However it does not on the FPGA and the SDF anotated simulation doesn't either. I get tons of setup violations regarding LUT and Block RAMs. I tried to constain harder like to 25ns whereas my clock period is 30ns but it wont work. The RAMs are not input and not output registered. I need them to be if possible. Why does the place and route tool does not notice that the RAM timing can not be met?
2nd problem: Right now the generate post place and route simulation tool fails. I get an error which i cannot solve: Release 6.3.03i - netgen G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Loading device database for application netgen from file "pcim_top.ncd". "pcim_top" is an NCD, version 2.38, device xcv300, package bg432, speed -6 Loading device for application netgen from file 'v300.nph' in environment /opt0/eda/xilinx/linux/xilinx. Loading constraints from file "pcim_top.pcf"... ERROR:Anno:207 - 6 block(s) were unexpanded, including the following: 'HAL_INST/initiator_inst/rsp_fifo_inst/full2_inst' (TYPE=equal) 'HAL_INST/initiator_inst/rsp_fifo_inst/full3_inst' (TYPE=equal) 'HAL_INST/initiator_inst/rsp_fifo_inst/full4_inst' (TYPE=equal) 'HAL_INST/initiator_inst/cmd_fifo_inst/empty2_inst' (TYPE=equal) 'HAL_INST/initiator_inst/cmd_fifo_inst/empty3_inst' (TYPE=equal) 'HAL_INST/initiator_inst/cmd_fifo_inst/empty4_inst' (TYPE=equal) Unexpanded blocks usually result from incomplete or erroneous configuration of the corresponding components in the .ncd file. ERROR:NetListWriters:528 - Unsuccessfull design annotation.
any idea?
I am using ISE 6.3. SImulator is cadence ncsim.
Thank you so much iam quite desperate.