Xilinx bitgen vs output file name

I'm using Xilinx 8.1 and would like to find a way to have bitgen create its output files with a different basename from the default.

It looks like ISE propagates the top level Verilog module as the basename for all the subsequent files. Is there any way to override this behaviour? I don't think the 'other bitgen command line options" menu choice works for this.

Any ideas?

Thanks!

John Providenza

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