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Xilinx Area Constraints for partial reconfiguration

Hello,

I read the XAPP 290 which provides guidelines for partial reconfiguration. I have a couple of questions with regard to some of the constraints imposed by xilinx.

  1. Can I not divide the FPGA into a set of rectangles and say that each of these rectangles are reconfigurable. If so how do I define the area constraints of the module?

2.Why is it that you cannot define a reconfigurable module to be a rectangular region? I am aware of the fact that Xilinx is a column based device, however if I can tolerate the overhead involved in reading the frames for all those columns and modifying just the rectangular region. Can this not be done?

To be more clear if we consider 4 CLB columns and asume that there are

3 reconfigurable modules present in those columns. Each of these modules extend three column width but the height of it are different. (imagine the modules are stacked one upon another). Now if I want to reconfigure one of the three modules then can I not read the bit stream from all the 4 columns modify the particular data in the frames corresponding to the module that I want to replace with another module and write back all the frames. Can this not be done?

  1. Why are the reconfigurable modules are to be constrained to just the horizontal boundary of 0,4,8 etc?

  2. The area group constraint says that you can constrain the area of the module within the particular region of the FPGA. However it does not ensure that the routing resources will be within the specified area. If we define a bounding box as the set of all routing and CLB resources then in the worst case how much more area can we expect that the routing resource will be extended to? For example I define a rectangular region of fixed length and width is there a safe assumption we can make that the design will not exceed this much percentage of width and this much percentage of length Can anyone please clarify my doubts?

Thanks

Reply to
Harish
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Sure, anything can be done. But Xilinx does not provide software to do it. You will have to do that yourself. The hard part is constraining

*BOTH* your module logic and routing to that rectangle.

Sure. How do you plan to implement this though? Are you going to write your own software?

Because the CLBs span that width, IIRC.

You are correct about the typical LOC constraints. I have not dug deeply enough into it to know how they contrain the routing to column boundaries, but they must have a special way of doing this to allow this to work at all. I also have no idea if you can use the same method to constrain routing to vertical regions which you would need to work with rectangles.

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Rick "rickman" Collins

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Reply to
rickman

Hello Rick,

Thanks for the reply. I hope Xilinx provides with the information as how they restrict the resources within the column. With regard to the other questions I do plan to write my own software working on the top of Xilinx tools( I am still analyzing the issues associated with it)

Thanks Harish

Reply to
Harish

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