XIlinx 7.1i ISE problem with Spartan 3e design

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Guys/Gals,
I am primarily an Altera developer at work, so I have a lot more
experience with Quartus than ISE. (our site develops with both Altera
and Xilinx designs, but most of my projects have involved Altera
devices)

However, as the proud recipient of a Spartan 3E sample pack board, I
decided to give it a go. I am using the tool chain at work, because our
site has the 7.1 EDK and ChipScope tools installed. (EDK may be
overkill on a xc3s100e, but ChipScope seems like a useful tool) We
haven't licensed the 8.1i tool chain yet, so I don't have access to it
at work - though I can try it at home.

The problem is that the tool seems to have LOC's and BANK's confused.

I created a shell VHDL file that has all the I/O on the board defined,
and assigned each signal a static level just to get the project going.
I then started a new ISE project, told it to add my top-level VHD file,
and assigned the part. This all works fine, and the correct part number
is listed (xc3s100e-tq144).

Next, I run the "Assign Package Pins" to set the pinout. ISE creates a
blank .ucf file, and presents me with the PACE editor. This is where
the rub is. When I click on fields under LOC, I get bank numbers - not
pin locations. If I try to enter the pin location, the entry is
deleted.

So, I try to get fancy, and create my own .ucf file:

Net Clock_50     LOC = "122" | IOSTANDARD  = LVCMOS33 ;
Net FL_Status    LOC = "66"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<0>   LOC = "98"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<1>   LOC = "97"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<2>   LOC = "96"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<3>   LOC = "94"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<4>   LOC = "93"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<5>   LOC = "92"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<6>   LOC = "91"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<7>   LOC = "88"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<8>   LOC = "87"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<9>   LOC = "86"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<10>  LOC = "85"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<11>  LOC = "82"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<12>  LOC = "81"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<13>  LOC = "77"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<14>  LOC = "76"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<15>  LOC = "75"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<16>  LOC = "74"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<17>  LOC = "70"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<18>  LOC = "68"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<19>  LOC = "67"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<20>  LOC = "44"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Addr<21>  LOC = "83"  | IOSTANDARD  = LVCMOS33 ;
Net FL_Data<0>   LOC = "63"  | IOSTANDARD  = LVCMOS33      | PULLUP ;
Net FL_Data<1>   LOC = "89"  | IOSTANDARD  = LVCMOS33      | PULLUP ;
Net FL_Data<2>   LOC = "58"  | IOSTANDARD  = LVCMOS33      | PULLUP ;
Net FL_Data<3>   LOC = "54"  | IOSTANDARD  = LVCMOS33      | PULLUP ;
Net FL_Data<4>   LOC = "53"  | IOSTANDARD  = LVCMOS33      | PULLUP ;
Net FL_Data<5>   LOC = "52"  | IOSTANDARD  = LVCMOS33      | PULLUP ;
Net FL_Data<6>   LOC = "51"  | IOSTANDARD  = LVCMOS33      | PULLUP ;
Net FL_Data<7>   LOC = "50"  | IOSTANDARD  = LVCMOS33      | PULLUP ;
Net FL_Data<8>   LOC = "78"  | IOSTANDARD  = LVCMOS33      | PULLUP ;
Net FL_Data<9>   LOC = "84"  | IOSTANDARD  = LVCMOS33      | PULLUP ;
Net FL_Data<10>  LOC = "89"  | IOSTANDARD  = LVCMOS33      | PULLUP ;
Net FL_Data<11>  LOC = "95"  | IOSTANDARD  = LVCMOS33      | PULLUP ;
Net FL_Data<12>  LOC = "101" | IOSTANDARD  = LVCMOS33      | PULLUP ;
Net FL_Data<13>  LOC = "107" | IOSTANDARD  = LVCMOS33      | PULLUP ;
Net FL_Data<14>  LOC = "111" | IOSTANDARD  = LVCMOS33      | PULLUP ;
Net FL_Data<15>  LOC = "114" | IOSTANDARD  = LVCMOS33      | PULLUP ;
Net FL_WE_n      LOC = "103" | IOSTANDARD  = LVCMOS33 ;
Net FL_CE0_n     LOC = "104" | IOSTANDARD  = LVCMOS33 ;
Net FL_OE_n      LOC = "105" | IOSTANDARD  = LVCMOS33 ;
Net FL_Byte_n    LOC = "106" | IOSTANDARD  = LVCMOS33 ;
Net PortA<0>     LOC = "14"  | IOSTANDARD  = LVCMOS33 ;
Net PortA<1>     LOC = "15"  | IOSTANDARD  = LVCMOS33 ;
Net PortA<2>     LOC = "16"  | IOSTANDARD  = LVCMOS33 ;
Net PortA<3>     LOC = "17"  | IOSTANDARD  = LVCMOS33 ;
Net PortB<0>     LOC = "20"  | IOSTANDARD  = LVCMOS33 ;
Net PortB<1>     LOC = "21"  | IOSTANDARD  = LVCMOS33 ;
Net PortB<2>     LOC = "22"  | IOSTANDARD  = LVCMOS33 ;
Net PortB<3>     LOC = "23"  | IOSTANDARD  = LVCMOS33 ;
Net PortC<0>     LOC = "25"  | IOSTANDARD  = LVCMOS33 ;
Net PortC<1>     LOC = "26"  | IOSTANDARD  = LVCMOS33 ;
Net PortC<2>     LOC = "29"  | IOSTANDARD  = LVCMOS33 ;
Net PortC<3>     LOC = "32"  | IOSTANDARD  = LVCMOS33 ;
Net PortD<0>     LOC = "33"  | IOSTANDARD  = LVCMOS33 ;
Net PortD<1>     LOC = "34"  | IOSTANDARD  = LVCMOS33 ;
Net PortD<2>     LOC = "35"  | IOSTANDARD  = LVCMOS33 ;
Net PortD<3>     LOC = "40"  | IOSTANDARD  = LVCMOS33 ;
Net P1           LOC = "6"   | IOSTANDARD  = LVCMOS33 ;
NET P2           LOC = "10"  | IOSTANDARD  = LVCMOS33 ;
NET P3           LOC = "8"   | IOSTANDARD  = LVCMOS33 ;
NET P4           LOC = "12"  | IOSTANDARD  = LVCMOS33 ;
NET LED<1>       LOC = "142" | IOSTANDARD  = LVCMOS33 ;
NET LED<2>       LOC = "43"  | IOSTANDARD  = LVCMOS33 ;
NET LED<3>       LOC = "2"   | IOSTANDARD  = LVCMOS33 ;
NET LED<4>       LOC = "3"   | IOSTANDARD  = LVCMOS33 ;
NET LED<5>       LOC = "4"   | IOSTANDARD  = LVCMOS33 ;
NET LED<6>       LOC = "5"   | IOSTANDARD  = LVCMOS33 ;
NET LED<7>       LOC = "7"   | IOSTANDARD  = LVCMOS33 ;
NET Button       LOC = "18"  | IOSTANDARD  = LVCMOS33 ;
NET WE_A         LOC = "140" | IOSTANDARD  = LVCMOS33 ;
NET OE_A         LOC = "139" | IOSTANDARD  = LVCMOS33 ;
NET CSA          LOC = "135" | IOSTANDARD  = LVCMOS33 ;
NET LSBCLK       LOC = "134" | IOSTANDARD  = LVCMOS33 ;
NET MA1_DB<0>    LOC = "132" | IOSTANDARD  = LVCMOS33 ;
NET MA1_DB<1>    LOC = "131" | IOSTANDARD  = LVCMOS33 ;
NET MA1_DB<2>    LOC = "130" | IOSTANDARD  = LVCMOS33 ;
NET MA1_DB<3>    LOC = "129" | IOSTANDARD  = LVCMOS33 ;
NET MA1_DB<4>    LOC = "128" | IOSTANDARD  = LVCMOS33 ;
NET MA1_DB<5>    LOC = "126" | IOSTANDARD  = LVCMOS33 ;
NET MA1_DB<6>    LOC = "125" | IOSTANDARD  = LVCMOS33 ;
NET MA1_DB<7>    LOC = "124" | IOSTANDARD  = LVCMOS33 ;
NET MA1_AStb     LOC = "123" | IOSTANDARD  = LVCMOS33 ;
NET MA1_DStb     LOC = "113" | IOSTANDARD  = LVCMOS33 ;
NET MA1_Write    LOC = "117" | IOSTANDARD  = LVCMOS33 ;
NET MA1_Wait     LOC = "116" | IOSTANDARD  = LVCMOS33 ;
NET MA1_Reset    LOC = "56"  | IOSTANDARD  = LVCMOS33 ;
NET MA1_Int      LOC = "112" | IOSTANDARD  = LVCMOS33 ;
NET GPIO_CCLK    LOC = "71"  | IOSTANDARD  = LVCMOS33 ;
NET GPIN_0       LOC = "136" | IOSTANDARD  = LVCMOS33 ;
NET GPIN_1       LOC = "141" | IOSTANDARD  = LVCMOS33 ;
NET GPIN_p       LOC = "119" | IOSTANDARD  = LVCMOS33 ;
NET GPIN_n       LOC = "120" | IOSTANDARD  = LVCMOS33 ;

(Note, I had a technician at work route some unused I/O to the
connector)

This seems to work, until I get to the mapping phase, where EVERY
SINGLE LOCATION is invalid. I get a string of warning messages like the
following:

ERROR:MapLib:30 - LOC constraint 122 on Clock_50 is invalid: No such
site on the
   device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.

BTW - for owners of this board, Clock_50 is the 50MHz clock on GCLK4.

So, did I do something wrong, or is my install of ISE 7.1i fouled up? I
did a clean install of ISE 7.1i to a "virgin" machine (no other version
of ISE has ever been installed on this system) and applied SP4. I then
installed the EDK, and ChipScope.

Note, when I go into PACE, the pin data shows up in the correct column,
but if I try to change it, the field is erased as before.

Thanks!
-Seth


Re: XIlinx 7.1i ISE problem with Spartan 3e design
Hi,
For a SP3 TQ144 package I use UCF statements like:

NET "cpuData<0>"          LOC = P141     | IOSTANDARD=LVCMOS33 | SLEW=SLOW |
DRIVE=8;

Also make sure you are actually driving or reading the pin with your
design, otherwise the tools will strip it out and fail to attach the
LOC constraint. But in that case I think it gives a different error
message than the one you are getting...

Regards
Andrew

radarman wrote:
Quoted text here. Click to load it


Re: XIlinx 7.1i ISE problem with Spartan 3e design

Quoted text here. Click to load it

Thanks! That worked great. Apparently the 'P' is important.

However, I still don't know why I couldn't enter the information using
PACE. The drop-down boxes showed bank numbers, not pin numbers - and
the column for BANK was grayed out.

Still, typing the info directly into the .ucf is much quicker, so I'm
not that disturbed by that. (yet)

As an aside, I discovered that Digilent did some strange things when
they built this board. Half of the flash-bus is input-only. 2 of the 8
signals in MA1_DB are input-only. I would have dropped some of the
other signals to make all of the databus read-write - but hey, it was
free!

-Seth


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