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XIlinx 7.1i ISE problem with Spartan 3e design

Guys/Gals, I am primarily an Altera developer at work, so I have a lot more experience with Quartus than ISE. (our site develops with both Altera and Xilinx designs, but most of my projects have involved Altera devices)

However, as the proud recipient of a Spartan 3E sample pack board, I decided to give it a go. I am using the tool chain at work, because our site has the 7.1 EDK and ChipScope tools installed. (EDK may be overkill on a xc3s100e, but ChipScope seems like a useful tool) We haven't licensed the 8.1i tool chain yet, so I don't have access to it at work - though I can try it at home.

The problem is that the tool seems to have LOC's and BANK's confused.

I created a shell VHDL file that has all the I/O on the board defined, and assigned each signal a static level just to get the project going. I then started a new ISE project, told it to add my top-level VHD file, and assigned the part. This all works fine, and the correct part number is listed (xc3s100e-tq144).

Next, I run the "Assign Package Pins" to set the pinout. ISE creates a blank .ucf file, and presents me with the PACE editor. This is where the rub is. When I click on fields under LOC, I get bank numbers - not pin locations. If I try to enter the pin location, the entry is deleted.

So, I try to get fancy, and create my own .ucf file:

Net Clock_50 LOC = "122" | IOSTANDARD = LVCMOS33 ; Net FL_Status LOC = "66" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "98" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "97" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "96" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "94" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "93" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "92" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "91" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "88" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "87" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "86" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "85" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "82" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "81" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "77" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "76" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "75" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "74" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "70" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "68" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "67" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "44" | IOSTANDARD = LVCMOS33 ; Net FL_Addr LOC = "83" | IOSTANDARD = LVCMOS33 ; Net FL_Data LOC = "63" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data LOC = "89" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data LOC = "58" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data LOC = "54" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data LOC = "53" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data LOC = "52" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data LOC = "51" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data LOC = "50" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data LOC = "78" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data LOC = "84" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data LOC = "89" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data LOC = "95" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data LOC = "101" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data LOC = "107" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data LOC = "111" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data LOC = "114" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_WE_n LOC = "103" | IOSTANDARD = LVCMOS33 ; Net FL_CE0_n LOC = "104" | IOSTANDARD = LVCMOS33 ; Net FL_OE_n LOC = "105" | IOSTANDARD = LVCMOS33 ; Net FL_Byte_n LOC = "106" | IOSTANDARD = LVCMOS33 ; Net PortA LOC = "14" | IOSTANDARD = LVCMOS33 ; Net PortA LOC = "15" | IOSTANDARD = LVCMOS33 ; Net PortA LOC = "16" | IOSTANDARD = LVCMOS33 ; Net PortA LOC = "17" | IOSTANDARD = LVCMOS33 ; Net PortB LOC = "20" | IOSTANDARD = LVCMOS33 ; Net PortB LOC = "21" | IOSTANDARD = LVCMOS33 ; Net PortB LOC = "22" | IOSTANDARD = LVCMOS33 ; Net PortB LOC = "23" | IOSTANDARD = LVCMOS33 ; Net PortC LOC = "25" | IOSTANDARD = LVCMOS33 ; Net PortC LOC = "26" | IOSTANDARD = LVCMOS33 ; Net PortC LOC = "29" | IOSTANDARD = LVCMOS33 ; Net PortC LOC = "32" | IOSTANDARD = LVCMOS33 ; Net PortD LOC = "33" | IOSTANDARD = LVCMOS33 ; Net PortD LOC = "34" | IOSTANDARD = LVCMOS33 ; Net PortD LOC = "35" | IOSTANDARD = LVCMOS33 ; Net PortD LOC = "40" | IOSTANDARD = LVCMOS33 ; Net P1 LOC = "6" | IOSTANDARD = LVCMOS33 ; NET P2 LOC = "10" | IOSTANDARD = LVCMOS33 ; NET P3 LOC = "8" | IOSTANDARD = LVCMOS33 ; NET P4 LOC = "12" | IOSTANDARD = LVCMOS33 ; NET LED LOC = "142" | IOSTANDARD = LVCMOS33 ; NET LED LOC = "43" | IOSTANDARD = LVCMOS33 ; NET LED LOC = "2" | IOSTANDARD = LVCMOS33 ; NET LED LOC = "3" | IOSTANDARD = LVCMOS33 ; NET LED LOC = "4" | IOSTANDARD = LVCMOS33 ; NET LED LOC = "5" | IOSTANDARD = LVCMOS33 ; NET LED LOC = "7" | IOSTANDARD = LVCMOS33 ; NET Button LOC = "18" | IOSTANDARD = LVCMOS33 ; NET WE_A LOC = "140" | IOSTANDARD = LVCMOS33 ; NET OE_A LOC = "139" | IOSTANDARD = LVCMOS33 ; NET CSA LOC = "135" | IOSTANDARD = LVCMOS33 ; NET LSBCLK LOC = "134" | IOSTANDARD = LVCMOS33 ; NET MA1_DB LOC = "132" | IOSTANDARD = LVCMOS33 ; NET MA1_DB LOC = "131" | IOSTANDARD = LVCMOS33 ; NET MA1_DB LOC = "130" | IOSTANDARD = LVCMOS33 ; NET MA1_DB LOC = "129" | IOSTANDARD = LVCMOS33 ; NET MA1_DB LOC = "128" | IOSTANDARD = LVCMOS33 ; NET MA1_DB LOC = "126" | IOSTANDARD = LVCMOS33 ; NET MA1_DB LOC = "125" | IOSTANDARD = LVCMOS33 ; NET MA1_DB LOC = "124" | IOSTANDARD = LVCMOS33 ; NET MA1_AStb LOC = "123" | IOSTANDARD = LVCMOS33 ; NET MA1_DStb LOC = "113" | IOSTANDARD = LVCMOS33 ; NET MA1_Write LOC = "117" | IOSTANDARD = LVCMOS33 ; NET MA1_Wait LOC = "116" | IOSTANDARD = LVCMOS33 ; NET MA1_Reset LOC = "56" | IOSTANDARD = LVCMOS33 ; NET MA1_Int LOC = "112" | IOSTANDARD = LVCMOS33 ; NET GPIO_CCLK LOC = "71" | IOSTANDARD = LVCMOS33 ; NET GPIN_0 LOC = "136" | IOSTANDARD = LVCMOS33 ; NET GPIN_1 LOC = "141" | IOSTANDARD = LVCMOS33 ; NET GPIN_p LOC = "119" | IOSTANDARD = LVCMOS33 ; NET GPIN_n LOC = "120" | IOSTANDARD = LVCMOS33 ;

(Note, I had a technician at work route some unused I/O to the connector)

This seems to work, until I get to the mapping phase, where EVERY SINGLE LOCATION is invalid. I get a string of warning messages like the following:

ERROR:MapLib:30 - LOC constraint 122 on Clock_50 is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

BTW - for owners of this board, Clock_50 is the 50MHz clock on GCLK4.

So, did I do something wrong, or is my install of ISE 7.1i fouled up? I did a clean install of ISE 7.1i to a "virgin" machine (no other version of ISE has ever been installed on this system) and applied SP4. I then installed the EDK, and ChipScope.

Note, when I go into PACE, the pin data shows up in the correct column, but if I try to change it, the field is erased as before.

Thanks!

-Seth

Reply to
radarman
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Hi, For a SP3 TQ144 package I use UCF statements like:

NET "cpuData" LOC = P141 | IOSTANDARD=LVCMOS33 | SLEW=SLOW | DRIVE=8;

Also make sure you are actually driving or reading the pin with your design, otherwise the tools will strip it out and fail to attach the LOC constraint. But in that case I think it gives a different error message than the one you are getting...

Regards Andrew

radarman wrote:

Reply to
Andrew FPGA

Thanks! That worked great. Apparently the 'P' is important.

However, I still don't know why I couldn't enter the information using PACE. The drop-down boxes showed bank numbers, not pin numbers - and the column for BANK was grayed out.

Still, typing the info directly into the .ucf is much quicker, so I'm not that disturbed by that. (yet)

As an aside, I discovered that Digilent did some strange things when they built this board. Half of the flash-bus is input-only. 2 of the 8 signals in MA1_DB are input-only. I would have dropped some of the other signals to make all of the databus read-write - but hey, it was free!

-Seth

Reply to
radarman

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