Xilinx 6.2 to 6.3 upgrade brakes soc

Garbled UART output sounds like the baudrate may be incorrect. Maybe the UART-settings somehow got lost/changed during the upgrade? Or maybe they changed the name of the parameter that sets the baudrate in the latest version of the UART-core. Is the UART the only problem and everything else is working fine?

cu, Sean

Sorry, I was not very clear. The UART prints half of the message ok, than skips a lot than again a few readable words ...

I did check all the obvious things like baud rate etc. Thats not it. There seems some fundamental difference. The SoC seems to "hang" as well. Like may be something in the software changed ... it still does compile clean, and I did re-compile everything ... I spend two days trying to figure out what was wrong, than switched back to EDK 6.2.

Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

Your Partner for IP Cores, Design, Verification and Synthesis

...another sad story...

I think I can honestly say that I have spent at least 6 full weeks "fighting with EDK".

My estimate is that anyone who is responsible to maintain several EDK based SoC systems should count with minimum 1 week of extra time spent fixing up the projects when doing minor updates of EDK.

That is sad. Its wasted time. Time that no-one pays for. Maybe the situation gets better with EDK 7, I can only hope.

The above is my opinion and I stick to it. Maybe others have been more lucky, but I started with V2PDK 1.5 then EDK, pretty much all versions used! There is no way not to update and update has always been painful.

Antti

It doesn't surprise me. It seems everytime I've upgraded, something breaks, an IP goes to deprecated, goes obsolete, they find a new way to connect it. Sounds like your problem is more insideous. I've gone to the Memec sight, sometimes they have revisions to their reference designs that helps me figure out the new hard to find MHS syntax for different configurations. I've skipped the MicroBlaxe update cycle for EDK6.2, believing it was a waste of time since it would probably break when I upgraded to EDK6.3. Maybe it was the right decision.

I looked at the below sight, and they have not posted an upgrade to EDK6.3i either.

I realize the above is not much help, but I appreciate your frusteration.

Good luck,

-Newman

Rudolf, If you had the old EDK6.2i elf file and the EDK6.3i elf file, perhaps you could do a mb-objdump on both and then do a diff. The differences may provide a clue to where the problem may be, or maybe not. I read something about EDK6.3 transitioning to an Eclipse based look and feel software environment, and that there is a graphical linker tool now. Maybe your software suspicions are justified.

-Regards

Newman

I just upgraded 6.2 to 6.3 and am seeing the same symptoms. Garbled/missing console output and random resets/crashes. If I compile my code under EDK 6.2, it runs fine on the FPGA image created by EDK

6.3. Also, running 6.3 compiled code on a 6.2 FPGA image results in the same misbehavior. I suspect bugs in the GNU tools or libraries.

I fixed the console issue by turning off the "Global Pointer Optimization" and by using xil_printf in place of printf. However, even with these changes or with optimization turned off completely, I still get crashes/resets.

I have opened a Webcase with Xilinx support and will post any results here.

Joe