We are considering a change to the IO standard used for the QDR-II interface (1.5V HSTL Class 1 instead of 1.8V HSTL Class 1 (1.8V)). Xilinx has not created any demo boards that use the 1.5V interfaces, but they claim that it should work fine.
Have any of you completed a Xilinx design that uses the 1.5V interfaces (for QDR-II) or know of a successful development?