A couple of months ago I had to move up to ISE 8.2 once 7.1 stopped meeting my timings. Since I moved I have had nothing but problems with project files and their corruption. I have finally settled on 8.2.3 as it appeared more stable than older patched versions. 8.2.0 was dire.
The project file corruptions seem to occur randomly and will do various things, such as remove all files from the project (and not let you add them back), or not let you edit coregen parts, or a host of other things.
Re-creating a project each time seems very laborious. Does anyone have any shortcuts to do this? Is there a TCL script that can be run? Archiving and Project Cleanup don't help.
The project is a mix of VHDL, verilog and coregen parts (xaw and xco).
Why can't they just implement project files as text files and let you control them by hand?
A couple of months ago I had to move up to ISE 8.2 once 7.1 stopped meeting my timings. Since I moved I have had nothing but problems with project files and their corruption. I have finally settled on 8.2.3 as it appeared more stable than older patched versions. 8.2.0 was dire.
The project file corruptions seem to occur randomly and will do various things, such as remove all files from the project (and not let you add them back), or not let you edit coregen parts, or a host of other things.
Re-creating a project each time seems very laborious. Does anyone have any shortcuts to do this? Is there a TCL script that can be run? Archiving and Project Cleanup don't help.
The project is a mix of VHDL, verilog and coregen parts (xaw and xco).
Why can't they just implement project files as text files and let you control them by hand?
The 8.2 project navigator can still read the old text style .npl files. If you have a copy of 6.3 or older ISE you can see how these project files look. There is a caveat. When you open a .npl file from 8.2, ISE not only converts the project to the new format and creates an .ise file, but it also trashes the .npl file. So always keep another copy for re-building the project after a crash.
I have routinely started saving a copy of the .ise project away so that when ISE 8.2.03 trashes the file, I can copy it back. This has saved me several times recently.
Navigator is one buggy tool. There is a tcl script to let you export the file names from the binary database, but my experiments show you can't use it to import files into an ise project if they don't already exist in the project. Also, the tcl script requires that the .ise project exist already.
I hope the 9.x release of the tools is better than 8.x
I am still using 8.1sp3 (project constraints), and I generally work around this bt creating a batch file which calls ngdbuild, map, par, etc. in turn. The batch file is based on the log file created from the initial run with the project file.
a) Use a good version control system, such as CVS or SVN, and then revert to a good version whenever you run into corruption or b) Save a copy of the project when it is working, and then copy it back when things stop working.
a) is what you should do. b) is what you will do now that I've suggested it. a) is what you will eventually do.
Because they haven't yet learned the lesson that ISE designers tend to learn eventually. Text file project definitions always rise to the top of the users' wish list eventually, even though it is initially easier for the tool developers to just write() the binary structures into a file.
--
David M. Palmer dmpalmer@email.com (formerly @clark.net, @ematic.com)
I believe the original files were ASCII. The new binary .ise format is an "improvement". I think this was a huge mistake, the project file should be text - easily archived, documented, modified, etc. The binary file =is a nightmare for users.
You could write a Tcl script to create and recreate your project file. Run a Tcl script like the example below rather than directly launching ISE. This example script creates a project, runs the design, and then launches ISE. It also uses two .ucf file, one of which might have the timing information, and other might have the placement information.
-- Phil Hays
Example follows:
############################################################################### # Created by Phil Hays, Xilinx # Setup Xilinx environment, then run from Unix with "xtclsh dice.tcl" # # This Tcl script will implement a design and load it in the S3E FPGA on # the Spartan 3E Starter Kit Board # # There are two ucf files, one for pins and one for timing # ############################################################################### # Contact : e-mail snipped-for-privacy@xilinx.com # phone + 1 800 255 7778 # # Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are # provided to you "as is". Xilinx and its licensors make and you # receive no warranties or conditions, express, implied, # statutory or otherwise, and Xilinx specifically disclaims any
# implied warranties of merchantability, non-infringement, or # fitness for a particular purpose. Xilinx does not warrant that # the functions contained in these designs will meet your # requirements, or that the operation of these designs will be # uninterrupted or error free, or that defects in the Designs # will be corrected. Furthermore, Xilinx does not warrant or # make any representations regarding use or the results of the # use of the designs in terms of correctness, accuracy, # reliability, or otherwise. # # LIMITATION OF LIABILITY. In no event will Xilinx or its # licensors be liable for any loss of data, lost profits, cost # or procurement of substitute goods or services, or for any # special, incidental, consequential, or indirect damages # arising from the use or operation of the designs or # accompanying documentation, however caused and on any theory # of liability. This limitation will apply even if Xilinx # has been advised of the possibility of such damage. This # limitation shall apply not-withstanding the failure of the # essential purpose of any limited remedies herein. # # Copyright (c) 2006 Xilinx, Inc. # All rights reserved # ############################################################################### # Version 1.0 - 19-Oct-2006 # Initial version ###############################################################################
############################################################################### # MAIN ############################################################################### # Modify the project settings for the specific design # # Make sure there are no files in the build directory that you may want to # keep, as this TCL script cleans that directory by default! ###############################################################################
set PROJECT dice; # CHANGE THIS TO MATCH YOUR NAME !!!
if {[file exists [file join ".." bld]]} { puts "Deleting All Existing Project Files" # Perhaps ask ok here?? # Or perhaps skip project creation if project exists?? file delete -force [file join ".." bld] } puts "Creating New Project directory..." file mkdir [file join ".." bld]
############################################################################### # Put two ucf file into one. # This could be made as complex as required, however for demonstration it is # just a simple copy. ###############################################################################
puts "Creating New UCF file..."
set tempucf [file join ".." bld temp.ucf] set outfile [open $tempucf "w"] set infile [open "dice.ucf" "r"] while {![eof $infile]} { puts $outfile [gets $infile] } close $infile set infile [open "time.ucf" "r"] while {![eof $infile]} { puts $outfile [gets $infile] } close $infile close $outfile # cd .. cd bld project new $PROJECT.ise project set family spartan3e project set device xc3s500e project set package fg320 project set speed -4
############################################################################### # Modify the xfile add argument for the source files in the design ###############################################################################
############################################################################### # Set optional implementation options here. There is a problem with setting # project properties that at least one source must be added to the project # first. Therefore, the "project set" commands are after the "xfile add" # commands. ###############################################################################
puts "Setting Project Properties..."
project set "Optimization Effort" High project set "Cores Search Directories" ../src project set "Read Cores" true ;# default is true, don't need to set project set "Macro Search Path" ../src project set "Map Effort Level" High project set "Perform Timing-Driven Packing and Placement" 1 project set "Place & Route Effort Level (Overall)" High # Do not generate the default post place static timing report project set "generate post-place & route static timing report" false
############################################################################### # Run the design. ###############################################################################
process run "Implement Design" puts "Implement design done" process run "Generate Programming File" puts "Bit file ready!"
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here.
All logos and trade names are the property of their respective owners.