Hi all,
I've got a design that can be built in 2 different configurations, controlled via a VHDL constant / if-generate in a sub-module. Each configuration uses a particular set of I/O pins and leaves the others dangling. The Xilinx tools won't let me generate a bit file for this design.
ERROR:PhysDesignRules:10 - The network is completely unrouted.
I've tried tri-stating the unused I/O pins (pin
I am not sure if Xilinx's KEEP attribute might help or not.. Please check the Xilinx's constraints Guide, may be that might help you.
#################################################### Eg: in UCF -- NET "xyz" KEEP; ####################################################
-- parag
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