XEM3010

Hi, i am configurating the PLL of my FPGA board to achieve a higher frequency. The master clock frequency of it is at 100 MHz. I am trying to divide it to attain 800 MHz. May i know is this possible, since i am able to divide it in the PLL configuration? However, my output is distorted. May i know if this is due to the PLL configuration limit (unable to divide more than 4) or due to my oscilloscope? Please advise. Thank you.