.xco file and vcs verilog compiler

coregen FIFOs and such. I am using vcs compiler from synopsys. This compiler does not recgonize the xco files. Is there any way I can convert .xco file into verilog file using Xilinx coregen?

coregen fifo and instead it has the .xco file. Is there any advantage in doing so?

simulation. vcs compiler is able to compile the xilinx primitves .v files provided by Xilinx.

Coregen actually creates a verilog file for simulation. This file does not contain synthesizable code, however. If you only need the verilog for simulation, Coregen should be enough. If you want synthesizable verilog, you'll need to write your own or find another solution.

HTH, Gabor

r coregen FIFOs and such. I am using vcs compiler from synopsys. This compi= ler does not recgonize the xco files. Is there any way I can convert .xco f= ile into verilog file using Xilinx coregen?

for coregen fifo and instead it has the .xco file. Is there any advantage = in doing so?

imulation. vcs compiler is able to compile the xilinx primitves .v files pr= ovided by Xilinx.

You can run coregen in batch mode to generate simulations files from .xco files:

The table below lists the options to the coregen command.

Option Description

-b Invokes the CORE Generator=99 in batch mode and executes the commands in the specified command file during the batch mode run. The command_file_name argument specifies the path to the command file to be executed.

XCO files are commonly specified as the argument to the -b option, but you can specify any file containing valid CORE Generator commands.

Cheers, Jim