Hello all, First of all, I understand the best way to have a solution is to start a webcase and I am doing it right now. But like normal days I need to solve this issue asap and thought to ask the list as well. I have a design with a CPLD, a Spartan3 (XC3S400) and a XCF02S memory on the JTAG chain. I cannot see the memory in the JTAG chain, only the CPLD and FPGA. When doing a Get Device ID on any of these devices it says there is a wrong ID.
Before jumping on PCB or other cuases I have to say this design has already worked in the previous board spin. Though, there are two important differences:
1) The previous FPGA was an XC3S200. Same package. 2) The FPGA power supply is different. In the good (previous spin) board the 2.5V and 1.2V were from the 5V supply. Both 5V and 3V3 supplies are DC-DC converters from a single 28V power rail. In the new spin the 2.5V and 1.2V are from 3V3 supply (because 5V supply must be off some times during the equipment normal operation).The 3V3 ramp is about 700us long.
I have found some data in the internet that suggest the VCC ramp could make the memory to do not run JTAG interface properly. Other documents talk about the Reset/OE pin that must rise fast or the internal data can shift some bits causing failure in the configuration (but it assumes the JTAG is okay).
The board is ok. All connections were checked. The components seems ok and the memory was already replaced (just in case). The chain is: TDI- XCF02S-FPGA-CPLD-TDO. The XCF02S' TDO pin shows activity during the chain innitialization, like other devices's TDO pins.
I am not sure if the problem is with VCC ramp, with 2V5/1V2 FPGA supply (somehow driving the memory nuts) or has to do with new FPGA densisty that could drive more current in the power-up and make a dip in the VCC. Actualy, there is a flat portion during the 3V3 ramp but no dip as far as I can see with my digital scope.
Any hints on this case? Thanks, Augusto