- posted
19 years ago
I'm using Xilinx ISE4.1i schematic entry. The target device is XC4010E. In my design, there are several independent parts ( macro symbols ). When I modified one symbol's logic ( add or delete some gates/flip-flops ), other symbols' outputs changed. This problem occurs frequently. Someone tell me that reducing the used resource will be OK. So I download the design to XC2V1000 ( the used slices are 1%), but the problem still exists. Why small changes can affect other parts? I can't figure it out. Please help me.