Thanks for all your ideas on this matter.
There is no JTAG support on this device. All devices are programmed from an external computer using the Done/Prg', Reset, Data and Clock pins using the slave serial mode. The traces are daisy chained to each device and then terminated at the end of the bus. All devices are loaded with the same core using slave serial mode. Even if the loading state machine were some how stuck, needing more clock cycles to flush it, the programming does this upon each load sequence. Also, if you have the data sheet, on page 7-19, you will notice that during configuration, if the Reset pin is active, the configuration will abort and the init. sequence will start over.
The following is from the data sheet for the 3000:
"To initiate a re-programming cycle, the dual-function pin DONE/PROG must be given a High-to-Low transition. To reduce sensitivity to noise, the input signal is filtered for two cycles of the FPGA internal timing generator."
All of these pins are hard wired together. And once in the "locked" state, the device remains with the pin released. So, I am still able to pull the pin low to start a new download. Once the device is in the mode, it is almost like it behaves like it is no longer in the circuit. I am able to program all other devices in the chain.
The following is from the data sheet for the 3000:
"The FPGA tests for the absence of an external active Low RESET before it makes a final sample of the mode lines and enters the Configuration state. An external wired-AND of one or more INIT pins can be used to control configuration by the assertion of the active-Low RESET of a master mode device or to signal a processor that the FPGAs are not yet initialized. If a configuration has begun, a re-assertion of RESET for a minimum of three internal timer cycles will be recognized and the FPGA will initiate an abort, returning to the Clear state to clear the partially loaded configuration memory words. The FPGA will then resample RESET and the mode lines before re-entering the Configuration state. During configuration, the XC3000A, XC3000L, XC3100A, and XC3100L devices check the bit-stream format for stop bits in the appropriate positions. Any error terminates the configuration and pulls INIT Low."