XAUI v7.2 - timing issue - *channel bonding attributes*

I am using a XAUI core in my design for a PCIe board with a Xilinx Virtex - 5 LX110t FPGA. The board specifications require the GTP dual tiles of XAUI to be constrained to locations X0Y0 and X0Y7 which are far from each other on the FPGA. Due to this, the design does not meet timing. The user-guide for the rocketio transceivers suggests modification of channel bonding attributes of the GTP Dual tiles to meet timing. To try this out, the default channel bonding level for the 4 GTP tiles (2 GTP duals) was changed to 3,2,1,0 with 3 as the master tile. This design works fine in simulation, but does not meet timing. The timing error as seen on timing analyzer was due to the rxchanbondo signal.

The channel bond level was further changed to 5,4,1,0 with 5 as the master. Two pipeline stages were added for the rxchanbondo signal (between the tiles 4 and 1). This design meets timing, but does not work in simulation. All these changes were made to the rocketio_wrapper.v file in the XAUI core generated using coregen.

I feel that the wiring between the tiles in the rocketio_wrapper.v file needs to be modified to hook-up all the signals that may have been disturbed due to the addition of the two pipeline stages. Unfortunately I do not have a lot of experience working with rocketio transceivers and their channel bonding attributes which puts me in a state of bother while analyzing what signals need to be modified/ reassigned/patched between the gtp tiles.

I would appreciate any suggestions from anybody who has had experience working with XAUI, rocketio's and their channel bonding attributes.

Thanks for your help in advance

Reply to
explore
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Why are the GTP_DUAL sites constrained to X0Y0 and X0Y7, these are the worst possible locations to choose from. If the board hasn't gone through layout yet, can you change these to be adjacent locations?

Ed McGettigan

-- Xilinx Inc.

Reply to
Ed McGettigan

Thanks for your response. Unfortunately the board was not designed by us. This is an AVNET PCIe board that we happened to purchase a while ago. We hadn't put in the XAUI core until recently. Now we are forced to use the same GTP locations specified in the AVNET user guide. We were suggested by Xilinx support that we can use the flexibility of channel bonding available with rocketio's to try and make timing and this is the reason we are still hopeful of finding a solution to it. They also told us that some people were successful in making changes to the channel bonding in AURORA cores and the design to meet timing when they had a similar problem. As I mentioned earlier, the design meets timing when the tiles have channel bonding levels of 5,4,1,0 with 2 pipeline stages for rxchanbond signals, but I do not get to see it work in simulation. Would like your suggestion/ inputs on this.

Thanks for your time once again.

--Chethan

On Jun 16, 7:31=A0pm, Ed McGettigan wrote:

Reply to
explore

Ok, I understand now. I hope that when you take the design forward to your own platform that you clean this up and don't follow this design.

I was not familiar with this particular board, but I was able to determine that you are using the Avnet AES-XLX-V5LXT-PCIE110-G board and after getting the schematics it does show that the XAUI/CX4 interface that you are trying to use is split across the device using X0Y0 and X0Y7.

There are a couple of issues with this board design, but I will address your channel bond timing issue first.

You can make this timing work, but you have to insert additional registers in the RXCHBONDO[2:0] to RXCHBONDI[2:0] path. These ports use the faster 10-bit RXUSRCLK clock that will be running at at 312.5MHz in your application. My guess is that you will need at least 2 register stages to get across the device at this frequency and you made need three as the clock-to-out on RXCHBONDO and the setup into RXCHBONDI are long with respect to a 312.5 MHz clock.

You should place absolute placement LOC attributes on these registers to ensure that MAP doesn't pack the stages into the same slice and you get the spread that you need. After you have the timing working you will then need to set the correct CHAN_BOND_LEVEL value for each lane based on the number of stages that you used. This is describe in the GTP User Guide (UG196) Configurable Channel Bonding section.

In addition to channel bonding issue you also have two other issues with this board that impact your XAUI design.

1) You need to use two REFCLK sources, one for each GTP_DUAL. The board supports it, but you will likely need to update the XAUI source to add the second set of inputs to one of the GTP_DUALs. 2) The P/N nets are swapped for some of the pairs. The schematic indicates that you need to set the TXPOLARITY0 and RXPOLARITY0 on X0Y7 and TXPOLARITY1 on X0Y0 to 1 (default is 0).

Good luck.

Ed McGettigan

-- Xilinx Inc.

Reply to
Ed McGettigan

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