Hello,
I need to use a blockram as a FIFO to port data from one clock domain to another. I created a blockram with help of the language template. This blockram is recognised by the XST synthesiser. The dual clock is also recognised after a small modification. The next problem is to describe a databus width conversion. There is a 32 bit processor bus on one side and a
1 bit serial output on the other side. This is no problem with a library element or a blockram instance from the coregen. I don't like the coregen modules because it is not easy to back-up your sources or transport them to another PC. The library instances make the code less portable. Is there a way to describe the width conversion in VHDL without creating extra logic outside of the blockram?Thanks, Mark