My target board is virtex 4 and I'm trying to simulate multi microblaze processors. I am adding cache controllers to my design which will cache DDR SDRAM. I've prepared cache controller module for the same. This cache controller is connected to my microblaze processor through an OPB bus (processor is master and cache controller is slave on this OPB). And the same cache controller is connected to DDR SDRAM through another OPB bus (cache controller is master and DDR SDRAM is slave on this OPB). So in 'mpd' file of my cache controller I've two sets of OPB ports. 1) OPB ports which are used by the master (This is for cache controller - DDR SDRAM interface) 2) OPB ports which are used by the slave (This is for processor - cache controller interface).
I'm giving the ports section of the mpd file of the cache controller below MSOPB is the opb bus between cache controller and DDR SDRAM. SOPB is the opb bus between processor and cache controller.
## Ports PORT OPB_Clk = "", DIR = I, SIGIS = Clk, BUS = MSOPB:SOPB PORT OPB_Rst = OPB_Rst, DIR = I, SIGIS = Rst, BUS = MSOPB:SOPB PORT Sl_DBus = Sl_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB PORT Sl_errAck = Sl_errAck, DIR = O, BUS = SOPB PORT Sl_retry = Sl_retry, DIR = O, BUS = SOPB PORT Sl_toutSup = Sl_toutSup, DIR = O, BUS = SOPB PORT Sl_xferAck = Sl_xferAck, DIR = O, BUS = SOPB PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:(C_OPB_AWIDTH-1)], BUS = SOPB PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = SOPB PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB:SOPB PORT OPB_RNW = OPB_RNW, DIR = I, BUS = SOPB PORT OPB_select = OPB_select, DIR = I, BUS = SOPB PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = SOPB PORT M_ABus = M_ABus, DIR = O, VEC = [0:(C_OPB_AWIDTH-1)], BUS = MSOPB PORT M_DBus = M_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB PORT M_BE = M_BE, DIR = O, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = MSOPB PORT M_busLock = M_busLock, DIR = O, BUS = MSOPB PORT M_request = M_request, DIR = O, BUS = MSOPB PORT M_RNW = M_RNW, DIR = O, BUS = MSOPB PORT M_select = M_select, DIR = O, BUS = MSOPB PORT M_seqAddr = M_seqAddr, DIR = O, BUS = MSOPB PORT OPB_errAck = OPB_errAck, DIR = I, BUS = MSOPB PORT OPB_MGrant = OPB_MGrant, DIR = I, BUS = MSOPB PORT OPB_retry = OPB_retry, DIR = I, BUS = MSOPB PORT OPB_timeout = OPB_timeout, DIR = I, BUS = MSOPB PORT OPB_xferAck = OPB_xferAck, DIR = I, BUS = MSOPB
In the hdl files (user_logic.v and cache_cntlr.vhdl) of the cache controller I've defined signals according to the ports on the corresponding bus. The problem is that while generating the netlist, wrapper file named "cache_cntlr_1_wrapper.vhd" is giving the error:
"No default binding for component: . Ports are not on the entity."
Now, as I said before, I've defined these ports in the mpd file and then defined necessary user ports in the user logic file and vhdl file. I can't understand then how these ports are "not on the entity". Please help me understand my mistake. I'll be highly obliged.
Thanks.
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