Hi,
My name is Loo, I am fresh for FPGA and Wishbone. Currently, I am using the Opencore I2C with Wishbone interface for my project. However, I am facing some issue here. I hope someone there can help me.
I try to do the execise below: Example 1 Write 1 byte of data to a slave. Slave address = 0x51 (b"1010001") Data to write = 0xAC I2C Sequence:
1) generate start command 2) write slave address + write bit 3) receive acknowledge from slave 4) write data 5) receive acknowledge from slave 6) generate stop command Commands: 1) write 0xA2 (address + write bit) to Transmit Register, set STA bit, set WR bit.-- wait for interrupt or TIP flag to negate --
2) read RxACK bit from Status Register, should be '0'. write 0xAC to Transmit register, set STO bit, set WR bit.-- wait for interrupt or TIP flag to negate --
3) read RxACK bit from Status Register, should be '0'However, I cant get the correct waveform for SCL and SDA. Can someone tell me, what would be the timing diagram like for Wishbone input signal, which one I need to activated 1st and after that what should do. Pls help.