Hi everyone,
we are in the preliminary phase of the architecture definition for our system and we estimated FPGA resources (for a particular target) to be ~80% of the target's capabilities.
Being at such level at this stage is rather risky since we can easily find ourselves in deep troubles during implementation.
Unfortunately the target is an RTAX2000S, with the bigger sister being nearly as 3 times more expensive with only double the resources (RTAX4000S).
For this reason we are more incline to split the architecture into two FPGAs but that choice is certainly not free of hassles either.
Now comes the overhead of connection between the two devices and I came up with a very stupid idea: what if my SoC bus (possibly a wishbone) gets extended to the other FPGA as well?
With this approach I would simply move masters and slave around the two FPGAs without having to think too hard and they will interact as if they were sitting on the same fabric (except maybe for some extra latency).
Moreover, if we've been extremely good during our preliminary phase in anticipating the needed resources we can still fit everything in one FPGA without the need to change too much (just adding components on the bus).
Any opinion/experience/advice on the subject?
Al