Wire crossing in a large partially reconfigurable design.

Hi, there:

I am compiling a design which takes up 80% of the XC2V6000...After I put in the bus macros and run implementation, I found that there are a large number of wire crossings...For example, some VCC_FAKE_LEFT can route as long as three slices into the Right...vice versa...These wires just run into a switch boxes on the opposite side then flip back, but not connected to any slices I think...The same phenomenon never happened in my previous design which only uses 30% of the FPGA...

Is this acceptable for a partially reconfigurable design?

Best Regards, Kelvin

Reply to
Student
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Just as with sausages, you don't want to delve too deeply into the construction of an implemented FPGA. The router uses an iterative process which might not yield the perfect solution, but usually one that works. Even if it's not perfect, there's not much you can do about it. Just try some hand routing and you will be happy to let the router work on its own.

-Kevin

Reply to
Kevin Neilson

This is an artifact of Xilinx's place and route must finish faster philosophy. It used to be that if you got a good placement, the route would be near optimal for that placement. As devices got bigger, the route time increased too much for auto-placed designs, so now the router only works as hard as it needs to to meet timing. The result is you get many routes that do not take the shortest path, and worse, many nets become the critical path. In a densely placed design, the result is the routing gets congested and the tools may not find a routing solution that meets timing at all. Apparently, not many of Xilinx's big customers are running the FPGAs at the top of the performance envelope, because if they were I am sure this would be a much highr priority issue.

As for partial rec> Hi, there:

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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com
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"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

Reply to
Ray Andraka

I tried to define a guard area on the 8 slices where I placed the Bus Macros, basically I defined some additional area_groups to contain the placement of submodules, leaving the 8 slices gap not filled by much logic...

The wire crossing got better, but never gone...

What other tricks may I try?

Best Regards, Kelvin

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Reply to
Student

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