Hi, there:
I am compiling a design which takes up 80% of the XC2V6000...After I put in the bus macros and run implementation, I found that there are a large number of wire crossings...For example, some VCC_FAKE_LEFT can route as long as three slices into the Right...vice versa...These wires just run into a switch boxes on the opposite side then flip back, but not connected to any slices I think...The same phenomenon never happened in my previous design which only uses 30% of the FPGA...
Is this acceptable for a partially reconfigurable design?
Best Regards, Kelvin