Hi:
I am building my first Verilog project with Xilinx WebPack 5.2i.
I have a module test_delay8 that instantiates a module Delay8Bit, which in turn instantiates two further modules, an 8-bit comparator and an
8-bit counter, where the counter is inferred from the XST library.But I get lots of warnings about inputs and signals not used:
-------------------------------------------------------------------- Synthesizing Unit . Related source file is cb8ce.v. Found 8-bit up counter for signal . WARNING:Xst:647 - Input is never used. Summary: inferred 1 Counter(s). Unit synthesized.
Synthesizing Unit . Related source file is Delay8Bit.v. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. Unit synthesized.
Synthesizing Unit . Related source file is test_delay8.v. WARNING:Xst:646 - Signal is assigned but never used. Unit synthesized.
---------------------------------------------------------------------
The logic all seems to work, however.
What are these warnings all about? The signals certainly appear to be used from my perspective. I would like to understand how to code so that the warnings are not generated, since they are not confidence inspiring.
Thanks for assistance
Good day!
P.S. Here are all the modules if you'd like to see. Feel free to criticize my methods in addition to considering my original question:
module test_delay8(Trig_td, Out_td, Clk_td); input wire Trig_td, Clk_td; output wire Out_td;
wire [7:0] Delay_td;
assign Delay_td = 83;
Delay8Bit D1 (.Trig_in(Trig_td), .Out(Out_td), .Clk_in(Clk_td),
.Delay(Delay_td));
endmodule
module Delay8Bit(Trig_in, Out, Clk_in, Delay); input wire Trig_in, Clk_in; input wire [7:0] Delay; output wire Out;
wire [7:0] Qc; wire CompMatchOut; wire nowhere1, nowhere2; supply1 h;
CB8CE Counter1 ( .Q(Qc), .TC(nowhere1), .CE0(nowhere2), .C(Clk_in), .CLR(~Out), .CE(h) );
Compare8 Comp1 (CompMatchOut, Qc, Delay);
FDC FF1 ( .Q(Out), .C(Trig_in), .CLR(CompMatchOut), .D(h) );
endmodule
module Compare8(Q, A, B); output wire Q; input wire [7:0] A; input wire [7:0] B;
wire X7, X6, X5, X4, X3, X2, X1, X0;
xnor XNOR7 (X7, A[7], B[7]), XNOR6 (X6, A[6], B[6]), XNOR5 (X5, A[5], B[5]), XNOR4 (X4, A[4], B[4]), XNOR3 (X3, A[3], B[3]), XNOR2 (X2, A[2], B[2]), XNOR1 (X1, A[1], B[1]), XNOR0 (X0, A[0], B[0]);
and (Q, X7, X6, X5, X4, X3, X2, X1, X0);
endmodule
module CB8CE(Q, TC, CE0, C, CLR, CE); output reg [7:0] Q; output reg TC, CE0; input wire C, CLR, CE;
/* Here is the "Counter binary 8-bit async. clear with enable (CB8CE)" inference code from the Xilinx lib.pdf document: */ always @ (posedge C or posedge CLR) begin if (CLR) Q