why use an FPGA when a CPLD will do ??

Matt,

If you use a a cpld, you need to post in comp.arch.cpld

Aust> Hey guys/gals

lower cost, less power consumption, smaller size, easier configuration

There is a big difference in logic capabilities. Let's express that in the number of flip-flops or registers:

CPLDs are good for up to 200 flip-flops, they get disproportionally expensive for larger designs. Modern FPGAs start at 2,000 flip-flops, and go up to to 200,000 flip-flops, plus many other circuits, like RAM, multipliers etc.

CoolRunner CPLDs offer extremely low power c> Hey guys/gals

There is also the issue that FPGA's configuration data is stored in external FLASH where as CPLD's are programmed. It is actually quite easy to reprogram a FPGA on the fly and field update the external memory while the FPGA is still running. No special hardware or algorithms are required. Downloading a CPLD is usually done from a PC via a JTAG cable or via a External Chip Programmer.

Simon

using

There is no comp.arch.cpld

Hendra

I suspect he was being facetious, and just forgot the smiley ;)

Duane,

Yes, I apologize for my sarcasm.

I had just read the posting concerning newsgroups, and how to get the best answers from them. This post was a classic example of someone who had not even had the foresight to do any research on their own.

Given that everyone who posts here has access to google (or any other search engine), it is generally annoying to see questions that could be answered by three minutes of browsing and reading.

Sarcasm is the weapon of the weak, and I should have been more civil,

Aust> Hendra wrote:

but sarcasm is so much better than a pointy stick.

Simon

The answer to the heading is "You wouldn't" - if 'a CPLD will do', in engineering terms means meet/exceed the price performance levels of a FPGA.

The more general answer, of when to choose FPGA or CPLD, changes over time. 10 years ago, CPLDs were cheap, non volatile logic, but most had High Iccs. FPGAs were all SRAM based, and had low Static Iccs.

Now, the distinction is much more blurred : # There are FPGAs with on Chip FLASH, [Lattice, Actel] # FPGA static Icc is no longer low, but can hit hundreds of mA (!) # Newest CPLDs from Altera, Lattice have FPGA fabric, but CPLD-like FLASH - but at the same time, they have moved up the 'smallest device' point, so there are no real low cost members in this family. # Lowest power devices are now the CMOS structure ones from Xilinx, Lattice, Atmel. # Above a certain Logic size, FPGAs tend to self-select over the thinning ranks of large CPLDs

In many cases, designs have BOTH CPLD and FPGA, and the CPLD can be used to Boot the FPGA, via cheaper memory, and/or to control power off, to have deeper sleep modes.

-jg

Hallo,

Simon Peacock schrieb:

This is wrong. At least if you accept other fpga vendors beside Xilinx

OK.. I admit there are a few minor players who have flash based or fuse based FPGA's.. but then they aren't by definition field Programmable are they? They are in fact very large CPLD's as a FPGA is a Field Programmable Gate Array and Fuse devices aren't field programmable (or at least are only one-shot) FLASH devices could be considered field programmable... but some can't be used while a new program is getting uploaded. So that excludes them from what I would call Field Programmable.

Although some people might disagree.. I believe that A&X do hold the lions share of the market so RAM based rocks for now... until nano-tube becomes the fad.

Simon

external

update

hardware or

via a

The temptation is great,

Aust> but sarcasm is so much better than a pointy stick.

Certainly they are. Devices that are not "field programmable" are "mask programmable" at the time the chip is manufactured. That's been standard semiconductor industry terminology for more than thirty years.

The original field-programmable devices used NiCr fuses, which later gave way to TiW fuses, floating gate EPROM and EEPROM cells, and now flash memory and RAM-based parts.

Are some CPLD's more compatible with low-cost PCB's using fewer layers, than certain FPGA's? (memories of the spartan3 on four layers thread, where officially six was rated minimum)

Simon,

I admit that X&A are controlling the FPGA market, but stating that Flash based FPGA's are de facto not field Programmable is a bit of a strong statement. Both Actel and Lattice have flash based FPGA's, and Lattice provides a technique not seen from X&A before. They call it TFR or TransFR, but it is actually a manner of reconfiguring the FPGA while the system operates. I have not seen this from the big players. Maybe you will agree that in the telecom's world of today where five nines or six nines is the buzz word, both Altera and Xilinx are struggling to find an answer...

A humble FPGA designer

Luc

Hi,

Simon Peacock schrieb:

Yes, for sure. Field programmable has nothing to do with reconfiguration.

Ever tried to use a xilinx device while uploading them? If my memories correct, uloading with parallel port took over a minute for the first Virtex.

Ok, my answer on your last posting was a bit short, because a similar thread started in comp.lang.vhdl a few days ago :=). Sorry, should have used a full answer.

Originaly you had CPLD with less registers and weak routing abilities providing fast pathdelays against FPGAs with more registers and good routing but slow path delays.

Nowadays you differ between CPLD and FPGA mostly by marketing. The big CPLDs from Altera and Lattice are AFAIK FPGAs on a technological point of view. It seems to me only marketing to call them CPLD (maybe some customer are used to CPLDs and would never change to Fpga).

bye Thomas