Terrible! How may I optimize it in RTL codes?
assign tmp1 = en ? din_a_abs * din_b_abs : 16'b0; assign dout = sign ? ~tmp1 + 1'b1 : tmp1;
Best Regards, Kelvin
Terrible! How may I optimize it in RTL codes?
assign tmp1 = en ? din_a_abs * din_b_abs : 16'b0; assign dout = sign ? ~tmp1 + 1'b1 : tmp1;
Best Regards, Kelvin
As part of its logic simplifications, the synthesiser is expanding tmp1 in the expression being assigned to dout as follows:
assign dout = sign ? ~(en ? din_a_abs * din_b_abs : 16'b0) + 1'b1 : (en ? din_a_abs * din_b_abs : 16'b0);
and there are your two multipliers.
You need to tell the synthesiser not to expand the expression in this way. This can be done with a keep attribute on tmp1.
// synthesis attribute keep of tmp1 is true;
Regards, Allan.
Well probably you have a timing constaint that forces tmp1 to be duplicated to meet it, 1 inst has its output made -ve.the other as is. You may have a switch to stop this replication.
You could try putting the cond sgn negation in series with one of the
2 inputs or put it on the next pipeline or relax the timing, either way should give 1 mul.regards
johnjakson_usa_com
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