Hi, I have encountered a strange problem. Because an adder is called many times by different width functions, I program one, see bottom, it supports sign extension according to input width. One routine calls the adder fine, but it cannot be called by two times. That is the upper caller use RLOC or not, the following MAP error exists (it is only one of the many similars). From the error message, I still cannot understand the reason. It seems should be fine, because a slice does have two LUT and two CYs. What's the problem? Any suggestion is highly appreciated.
Section 1 - Errors
------------------ ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=hset, RLOC=X4Y1) which require the combination of the following symbols into a single SLICE component: LUT symbol "fir_0a/ADDER_3/INST_ADD[1].au_lut" (Output Signal = fir_0a/ADDER_3/lut_out) MUXCY symbol "fir_0a/ADDER_3/INST_ADD[1].au_mux" (Output Signal = fir_0a/ADDER_3/carry) XORCY symbol "fir_0a/ADDER_3/INST_ADD[1].au_xor" (Output Signal = fir_0a/MACC_adder_a2) LUT symbol "fir_0a/ADDER_3/INST_ADD[2].au_lut" (Output Signal = fir_0a/ADDER_3/lut_out) MUXCY symbol "fir_0a/ADDER_3/INST_ADD[2].au_mux" (Output Signal = fir_0a/ADDER_3/carry) XORCY symbol "fir_0a/ADDER_3/INST_ADD[2].au_xor" (Output Signal = fir_0a/MACC_adder_a2) The XORCY symbol fir_0a/ADDER_3/INST_ADD[1].au_xor can't be placed in the XORG site because the DI signal doesn't match the output signal of the function generator. Please correct the design constraints accordingly. ... loop_for0: for i in 0 to WIDTH-WIDTH0-1 generate array_preceding0(i)