Why the core dynamic power isn't 0 when the toggle rate is 0?

Rebecca,

Dynamic power is the power consumed when all clocks are toggling. When all clocks are at 0 hertz (not running), the power that is still there, is known as the static power.

In any design, with all data forced to 0's, and all flip flops with their clock enables disabled, but with the clock running, there will be dynamic power consumed from the clock tree toggling, and all of the logic in each flip flop that is still toggled by the clock, even without the flip flops changing state (a clock enable does not eliminate dynamic power).

Toggle rate is how often the data is changing. For example, 50% toggle rate means the data changes on every other clock.

So, the amount of logic and flip flops connected to a clock, the rate at which the nodes change state, and the frequency are all elements of the dynamic power.

The static power is from the leakage of the devices, and any constant current bias sources required for operation.

A toggle rate of 0%, is not a very interesting case (clocks are running, but nothing happens).

Austin

This may be a terminology issue. Is there a separate listing for Static Power ?

All devices have a power-drain of the form

Icc[Vcc.Temp.Max] = Icc.Static + Icc.Dynamic[Nodes.MHz]

Icc[Vcc.Temp.Typ] = Icc.Static + Icc.Dynamic[Nodes.MHz]

With this, if Mhz is zero, only the Icc.Static component should be included, and in modern FPGA that certainly IS 'still quite large'.

Even smaller CPLD devices that claim to be 'Zero power', really only get that Static.Icc somewhere under 100uA.

-jg

Thank you all very much for your detailed explanation. I know there is quite power consumption of the static power in the modern FPGAs. I am talking the dynamic power only here. Austin points that when toggle rate is 0, except power consumption of the clock tree, some internal logic, for example, the internal logic in a FF, will still change when clock toggled and induce power consumption. However, this case doesn't have much sense. I am asking this question because I am considering the design based on coarse-grained function blocks, where some blocks may be active and others may be idle. I was thinking to use the power consumption at togglerate=0 for those idle parts. In current FPGA, is there any technology to support a power-efficient solution for this case? For example, if the clock for each of the coarse-grain function block is provided via a DCM, can a particular clock be disabled and then no dynamic power will be consumed for the idle parts?

Thanks again, Rebbeca

Thank you all very much for your detailed explanation. I know there is quite power consumption of the static power in the modern FPGAs. I am talking the dynamic power only here. Austin points that when toggle rate is 0, except power consumption of the clock tree, some internal logic, for example, the internal logic in a FF, will still change when clock toggled and induce power consumption. However, this case doesn't have much sense. I am asking this question because I am considering the design based on coarse-grained function blocks, where some blocks may be active and others may be idle. I was thinking to use the power consumption at togglerate=0 for those idle parts. In current FPGA, is there any technology to support a power-efficient solution for this case? For example, if the clock for each of the coarse-grain function block is provided via a DCM, can a particular clock be disabled and then no dynamic power will be consumed for the idle parts?

Thanks again, Rebecca

Rebecca,

The only way to save power is to gate the clock, and turn it off before it gets to the global clock tree. This may be problematic for timing.

The Xilinx clock tree and the software already turns off unused leaves of the tree, so saving any power power will require shutting clocks off completely.

Aust> Thank you all very much for your detailed explanation. I know there is

Austin: Thank you very much for your reply, Rebecca

If you gate the clock externally to multiple clock inputs, with equal path length and gate delay outside, is there still internal clock skew between different clock inputs? A simple TTL clock gate shouldn't be so hard to do.

-- glen