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Why Spartan-3e is the best

Why Spartan-3e is the best ================== Antti Lukats 4.Nov 2005

(I was asked about why I think so in private, but I think my response could have more general interest so I am posting the reply to c.a.f.)

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At first look there differences between S3 and S3e may not be so significant however there are several small things that make Spartan-3e my fist choice (from current low-cost RAM based FPGA offerings).

1) as Spartan-3 was the first Xilinx silicon on new technology its kind of logical that Xilinx has fixed in Spartan-3e some issues related to the use of the new technology. So even if those are minor, there are still chances that S3e is somewhat better simply because Xilinx has had more experience with the technology being used.

2) pricing is promised a little lower, this is not so big deal, but still, its pretty much logical to prefer silicon with best price/performance ratio.

3) S3e configuration options are WAY superior over all other RAM based FPGAs currently in production. S3e is the only FPGA that:

  • can load not only from SPI Flash but also from Atmel Dataflash meaning that a it is the only FPGA around that can directly use an MMC (Atmel MMC form factor packaged 2/4/8 MByte Dataflash cards) like Flash card as its main configuration media. So a design with S3e and MMC Card socket can boot from the removabale flash media card. Note that the MMC Card socket inserion switch could overide the 'enable' of the additional on board memory so the SoC loaded from the inserted into socket Dataflash card could copy a new bitstream and OS image onto onboard flash, so next 'boot' without card inserted could come from on board DataFlash. Nice little feature.

  • can load from Parallel Flash, just like the oldies (eg Xilinx first FPGA's). This is VERY good feature as it allows cheap Flash ROMs to be used for both config and OS image.

  • has 'multi boot' option. In Parallel Flash loading mode S3e can request its own reconfiguration from alternative image.

--
compared to S3, S3e configuration interface allows the use
of SPI or Platform Flash for firmware storage without the
use of extra FPGA IO pin workaround.

S3e configuration is still way less flexible than I could
have designed, but its still the industries best at the moment.


4) S3e has LVDS input onchip termination. I have to admit that
I first found the low cost LVDS onchip termination feature in
Altera Cyclone-II but then I did re-found it in Spartan-3e as
well. It may not so sound like a nig deal, but its a nice
little additional feature that may save some PCB space.

5) Some nice new (compared to other Spartan FPGAs)
package combinations like:
*Largest fabric in VQ100
*Largest fabric in chip-scale package
*Largest fabric in FT256
*Largest fabric in non-BGA package

5) S3e starterkit from Avnet is selling at almost all
time low price of 69USD. (Futre did sell Cyclone kits
for $49 for a while but that kit did not look anything
I would spend money for). To get an eval board with
HS USB chip + FPGA for total cost of $69? Real candy.

6) There are possible some other nice new features
I have not discovered yet :)


Antti Lukats
Reply to
Antti Lukats
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Antti Lukats schrieb:

[snipped Lord's prayer]

Amen, Reverend Atti. Is it possible that you are obsessed by S3E?? C'mon, life goes on with and without S3E!! There other things that are important. Even in an engineers life, right?

Just my two(euro)cents Falk

Reply to
Falk Brunner

"Falk Brunner" schrieb im Newsbeitrag news: snipped-for-privacy@individual.net...

Hi Falk,

sure! Like going to movies with the family. "Little Ice-bear II" is on our family menu this afternoon, when Anna (2 years) wakes up from beaty sleep we go.

Antti

Reply to
Antti Lukats

Where did you see that? Looking at

formatting link
it seems only the two smallest models are available in VQ100 and TQ144 packages. The smallest package for the largest fabric is the FG320, right? The datasheet has the same information.

--- Jecel

Reply to
Jecel

formatting link

I think Antti meant that the 3e has the largest resource available in (any) QFP, not that the biggest s3e die goes into a QFP. ie it is more a LUT/package measure.

-jg

Reply to
Jim Granville

formatting link

yes Jim.

also that it has largest fabric in SAME package compared to S3 or other Xilinx FPGA.

as example VQ100 is really nice package very thin, so largest LUTs you get in VQ100 is S3e. etc..

worlds largest non BGA FPGA is Actel PA3-3000E I think.

Antti

Reply to
Antti Lukats

I realize that there are people out there that need the 1000+ pin packages that large-scale FPGAs offer... but I do wish that 2-5 million "gate" FPGAs would come in VQ100/144 packages. Personally, I'd love to have the capacity, but I really dont need (or want) the complexity and raw bandwidth of having to deal with several hundred (or a thousand) pins...

--
 [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax
Reply to
Tobias Weingartner

Just doesn't work that way unfortunately. The large fabric requires a large chip package to contain it. If you were to reduce the number of pin outs, the it would actually require an even larger chip package, as you would now have to add additional multiplexers etc to control the routing to the pins.

It would certainly be nice to have the additional logic in a smaller chip, but sorry to say this will only happen with geometry scaling, such as transition to 90nm and possibly to 65nm in the near future.

Reply to
Bevan Weiss

No, it wouldn't need any extra multiplexers. They would just not bond out as many of the pads to pins. They already do that to offer several package options for each FPGA.

The problem is that you don't save any significant cost by having the same size package with fewer balls or pins. So if the die size requires a package 20mm on a side, it may as well have more than 350 balls, even if some customers don't end up using all of them.

Reply to
Eric Smith

Unfortunately, the size of the cavity in those small packages is far too small to fit the die for the high density parts, and even if it did fit, you may have power dissipation issues as well.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759
Reply to
Ray Andraka

Thanks Jim and Antti for clearing that up.

-- Jecel

Reply to
Jecel

You've got an FPGA to help you route stuff... :)

--
 [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax
Reply to
Tobias Weingartner

There is a cost associated with me trying to acquire the resources and planning necessary to have a 1000+ pin FPGA mounted, routed and fed. On the other hand, 144 pins, or even 208 pins in a quad flat pack is pretty much doable...

Now, my naivitee(sp?) may show here, it may be that the power requirements for feeding such a beast can simply not be reliably met by the (T)QFP type of package...

--
 [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax
Reply to
Tobias Weingartner

any idea how big the dies are?, what will fit in a vq100, the only thing I could find on the web was something like 3x3mm sounds small for a 10x10 package?

-Lasse

Reply to
langwadt

That sounds about right to me. You've got to remember there's a tolerance on the die placement, so the interior die 'room' needs to be larger, then you've got the anchor space for the pins themselves and then the added space for the wirebonds.

BGAs can accommodate much larger dies given equivalent sizing to QFP etc etc. They don't require any room for wirebonds in almost all cases.

Reply to
Bevan Weiss

Guys, Here's the problem. These days all the parts are made on 90-130 nm processes. This means that the transistors switch very quickly. They also have lower power supply voltages, lowering the noise threshold. This means that even if the dice fitted the lead frame of a PQFP, the SI would be awful, probably such that the thing wouldn't work. There'd be bloody great inductors between the board ground and the die ground. The frequency isn't the limiting thing, it's the rise time. So, saying you're only gonna drive the outputs at 20 Mbps, doesn't fix the problem of sub ns rise/fall time. You could have small packages like Amkor's micro-lead-frame (MLF) QFN stuff with exposed paddles, but I guess if you don't like BGA, you're not gonna like that either. Cheers, Syms.

Reply to
Symon

Sure, but if the part doesn't fit in the die cavity of the package, it ain't gonna happen.

Reply to
Eric Smith

"Antti Lukats" schrieb im Newsbeitrag news:dki76s$cb1$ snipped-for-privacy@online.de...

Yes, you forgot to mention the extra fun you may have with the DCM / DFS >90MHz &&

Reply to
Raymund Hofmann

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