Why is Xilinx's WebPACK so inferior?

I've been using the Xilinx Webpack 8.2i since sometime in November, and I've become so irritated with their software that I'm about ready to just become a rabid Xilinx basher.

I've encountered uncountable crashes while actually trying to use their horribly clunky ISE. On a recent weekend I found four different internal errors in XST while using their command line tools.

For a product which boasts a copyright going back to 1995 -- that's a

12-year-old product -- it sure feels like alpha release software.

My most recent issue is the fact that most VHDL attributes are absolutely broken in the VHDL compiler. How on earth could such a horribly engineered and maintained product last for 12 years?

For example, this simple source will cause the XST product to produce one error. Only one. It gives up after one error, but if you reorder the assignments to 'i' and 'l' it will produce an error for that the other use of 'pred' as well.

entity main is Port (clk : in boolean); end main;

architecture are_xilinx_tools_inferior of main is

type logic_level is (unknown, low, undriven, high); type index is range 5 downto 0;

signal l : logic_level := undriven; signal i : index := 4;

begin

driver : process (clk) is begin if clk then i

Reply to
Taylor Hutt
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snipped rabid bashing...

Get a purchasing job at Cisco?

HTH, Syms.

p.s. You've really lasted since November? Dude, RESPECT! :-)

Reply to
Symon

Try the code in Altera's Quartus, and quote that - nothing like being seen to be last, to hurry someone along.... While you have Quartus up, you could even see how the new Cyclone III looks for the design. Mention that to Xilinx as well...

-jg

Reply to
Jim Granville

Taylor,

Well, Peter and I read the newsgroup, so we can provide an omudsman function.

Did you register? Did you get confirmation back? What was it that did not allow you to file a webcase?

If possible, send me what went wrong (links, steps taken, etc.).

With 250,000 seats of software, some people are able to file webcases...so it can't be completely broken! For example, I see the reports on what cases get filed, and what category they are assigned to (software, hardware, and so on).

One other comment: our synthesis tool (XST) was never meant to compete with the "real" tools that exist. XST is a vehicle for research into synthesis, where we have an opportunity to test how synthesis works with our FPGAs. We share all synthesis ideas and improvements with the "real" synthesis tool vendors, so that they may add value by performing more efficient synthesis using our devices. This is in no way an apology for bugs, but a statement of fact. XST is not intended to compete with "real" synthesis tools. It is made available in Webpack, as a means to allow others to get some feeling for the flow, and the potential. The XST team is dedicated to pioneering improvements, and they very much like to get feedback.

Efficient synthesis for things like our DSP48e, and other features are not trivial: and older tool may synthesis correctly, yet be horribly inefficient, and turn out huge areas and slow logic.

In any event, I will pass your issues along to the XST development team once I get the details of what did not work.

Austin

Reply to
Austin

Ombudsman...

Perhaps the previous spelling was a subconscious error?

In any event, send me the problems.

Austin

Reply to
Austin

Wow, I've been using xst (and webpack, base-x, and foundation) for years now and never once heard this. I've used it in over 20 designs, including some moderately-high-end virtex-4 stuff, and never had the slightest idea that I was using inferior tools.

Who makes these other synthesis tools? Are they expensive? Is this what happens when you do all of your engineering at a university?

...Eric

Reply to
jonas

I've maintained projects that targeted both X and A, and Quartus is leaps and heaps better (faster, much less buggy, and subjectively more user friendly). Austin's comment about not "competing with _real_ synthesizer" is odd to say the least. It sounds like an admision of defeat.

I'm not an A fan-boy. I'd be most happy if X improved ISE. I can imagine A getting design wins simply because ISE's effect on development time. Time to market is King.

Tommy

Reply to
Tommy Thorn

Wow.

Didn't Xilinx just add their own XST Simulation flow ?

- does that simulation capability, come into the same category, of "never meant to compete with the "real" tools" ?

How many staff do Xilinx have working on XST ? - do they concurr with Austin's statements above ?

-jg

Reply to
Jim Granville

Jim,

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If you read that page, it says what I just did, but in "marketese."

I quote:

"Xilinx uses XST as a proving ground for many of the innovative optimization ideas that Xilinx engineers have for improving HDL design flows for Xilinx devices. These improvements are then shared with Xilinx third party synthesis partners to ensure that anyone targeting Xilinx FPGAs as their solution can benefit from the best optimization the industry has to offer."

In other words, XST is a test vehicle where we are intentionally experimenting, in order to improve.

Austin

Reply to
Austin

Tommy,

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Might answer your questions.

Doesn't anyone even do a simple search before they type their response?

Austin

Reply to
Austin

And how is that in any way related to what I wrote? It doesn't address the slowness of ISE, all the many many bugs, and the broken user interface.

Doesn't anyone even read the articles they are replying to before they type their response?

Tommy

Reply to
Tommy Thorn

I worked a lot with ISE and only a few months with Quartus. I personally prefer Xilinx's devices but my short experience with Quartus was enough to make me feel like Quartus' synthesis flow is more mature. If I had to devices based on vendor-supplied tools, Quartus' more mature feel would offset my long-time Xilinx device preference. It is quite a shame that Xilinx puts so much (misplaced) effort in revamping their GUI but fail to fix the countless synthesis and GUI crash-bugs. Another annoyance with ISE is the wildly varying synthesis runtimes: running a small design (~20% of a V2P30) after cleaning may complete in 10-15 minutes one time and stall for

10-20 minutes to complete in 30+ the next time. Since these stalled runs often ran for over an hour or even failed to complete overnight a few times, I decided to start killing and restarting synthesis runs that deviated by more than 50% of an average run.

As for Austin's comment, I too remember reading that Xilinx cooperates closely with Synplicity to accelerate support for new FPGA features and optimizations. IIRC, that source said ISE exists primarily as an internal research tool, device/technology evaluation, characterization and as a basic vendor-supplied suite for people/companies that do not with to buy separate third-party synthesis packages. If you look at job postings, you will notice that practically 100% of Xilinx-oriented openings where FPGAs are used for complex processing post experience with Synplify as a must, hinting that relatively few serious Xilinx FPGA designs use ISE... this requirement appears to be far less frequent on Altera-oriented postings.

I really wish Xilinx would put more effort in making their synthesis tool-chain more stable before reworking GUIs and adding more features. Until then, Synplify is still an option (perhaps more along the lines of necessary) for more serious projects.

Reply to
Daniel S.

Well, I don't quite take the same meaning from the above web-statement, as I do from your posting :

"our synthesis tool (XST) was never meant to compete with the "real" tools that exist." " It is made available in Webpack, as a means to allow others to get some feeling for the flow, and the potential."

I see nothing in the web statement than excludes XST being a "real" tool, and in fact, you could read it that XST will always be "out ahead", because the _others_ have to follow the XST lead.

Your posting moves XST into the "not for real designs"/ [as is, where is] pigenhole, which is frankly startling.

Do those that work on XST really believe that, and apply that work-ethic to quality, and get given meagre resources by management that match the 'never meant to compete with the "real" tools' claim ?

Where does that leave your CPLD customers, for example ?

-jg

Reply to
Jim Granville

I wonder how many customers Xilinx has lost because they see that the performance of their parts with their own tools isn't as good as the competition...? I would think that many users will assume that Xilinx know their parts best, therefore their own software ought to get the most out of them, and so would look at competing devices before thinking of looking at third-party software.

Reply to
Mike Harrison

Very Interesting thread -

2 of the "other synthesis tools" are from Synplicity, and from Mentor (precision RTL) , and it just so happens both are supplied with Lattice ispLEVER tools - which offer a free d/l from the web -

sorry to hear that 250,000 Xilinx customers have been using an inferior synthesis tool all this time, by Xilinx' own admission -

All of the vendors work hard to supply reliable toolsets to their customer base - and judging from all the marketing foils on every vendor website, they have the best choice-

So the keyword here is choice - try out the toolsets offered free from each vendor website - all it'll cost is some bandwidth and disc space

-

Michael Thomas Lattice FAE -NY

Reply to
mikeandmax

I think what he means is quite simple:

XST is not Synplify (etc), and was not meant to replace it, since the most serious customers would be using something like that anyway. Rather than compete with those tool vendors, Xilinx actually shares information with them.

Reply to
cs_posting

Tommy,

Touche.

Austin

Reply to
Austin Lesea

Hi Austin,

is this your personal meaning, or official Xilinx? Do the Xilinx-software-team see their work in this context? Does this mean, that XST and/or ISE should not be used for serious work?

Thomas

Reply to
Thomas Entner

Thomas,

It is up to you. After you read the FAQ sheet, and the quote:

"Xilinx uses XST as a proving ground for many of the innovative optimization ideas that Xilinx engineers have for improving HDL design flows for Xilinx devices. These improvements are then shared with Xilinx third party synthesis partners to ensure that anyone targeting Xilinx FPGAs as their solution can benefit from the best optimization the industry has to offer."

Then make a decision. Is XST going to provide you with the value you seek? As you well know, sometimes one tool will provide a very different result from another tool. Synthesis is a complex and changing business, and recognition of elements, and targeting them to the most area efficient and speedy solution, is something that is non-trivial to do.

Some customers may be prototyping with FPGAs, and will not actually use them in production. For them, XST is (probably) completely capable of meeting their needs. Others will be trying to get the fastest possible logic, and pack the most into the smallest device, and they may end up trying several different tools (XST included) before they find the one that provides the best result.

Finally, there are those that go with a single vendor (Symplicity, for example), and are comfortable with the tools, and have developed a great deal of expertise in their use, and really do not want to try anything else as it would dilute their efforts.

If one read the FAQ, I doubt they would be complaining that "XYZ did not synthesize correctly in XST" as right there in the FAQ it states that it is not a 100% complete tool (recognizing all possible elements and constructs).

Austin

Reply to
Austin Lesea

MM,

We restrict webcases from being filed by students: (the only stated restriction)

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That said, the professors who use our components are allowed to file cases (they are instructed on how by the XUP program), and individuals who wish to file a webcase do have to register in a way that at least causes us to believe that they are a real or potential customer.

Austin

Reply to
Austin Lesea

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