I see it in many SDRAM controllers, e.g. ftp://ftp.xilinx.com/pub/applications/xapp/xapp608.pdf, and nobody explains WHY
The extranal feedback trace must equal to CK len. Ok. This means that SDRAM will be clocked in phase with the FPGA system. How does it ensure that cmd/addr arrives to SDRAM in proper time, half cycle earlier of CK?
In the more recommended xapp266 and xapp253, the external feedback is not used. Why? What is the purpose of the second, internal DLL? What should be the len of feedback in this case?
In these designs, the read DQ is clocked directly by DQS. Yet, DQ is changed simultaneously with DQS. This ensures the setup/hold violation! The "HOW TO USE DDR SDRAM" says: "when controller receives read data from DDR SDRAM, it will internally delay the received strobe to the center of the received data window." I do not see any delay!
Thanks