Why does Xilinx keep saying LVPECL_2.5 and _3.3V are identical?

qlyus,

The Virtex-II DC & Switching Characteristics data sheet mentions that "These values are valid when driving a 100 ? differential load only" suggesting that the LVPECL standard is supported for DIFFERENTIAL SIGNALS not the single ended you appear to be going toward. For a differential signal to work, both inputs have to be within the receiver's common mode range *and* have a differential swing at least as high as the receiver's minimum.

If you checked into the Virtex-II user's guide as the Virtex-II data sheet suggested, the write-up on Using LVPECL I/O in chapter 3 you'll see the implementation is entirely differential.

If you want to use single-ended LVPECL, you may need to do things a bit differently and derive your own numbers. Two approaches that *may* work for a pseudo-LVPECL would be to tie a center-crossing reference to *each* differential input pair or define the inputs as a reference-based single input standard with a slighlty different (but very close) center threshold reference.

John_H,

"100 ohm load" does not make difference here because both the tables for LVPECL_25 in V-II data sheet and the table for LVPECL_33 in V-II ds have this condition. From the tables, both common mode ranges

*and* diff swings are different each other, as least as I read. I am talking about Differential *and* Input only. I copied and pasted the tables as following:

LVPECL DC Specifications (LVPECL_25) VCCO = 2.5V VIH 0.8V(min) 2.0V(max) VIL 0.5V(min) 1.7V(max) Differential Input Voltage 0.100V(min) -(max)

LVPECL DC Specifications (LVPECL_33) VCCO = 3.3V VIH 1.49(min) 2.72V(max) VIL 0.86(min) 2.125V(max) Differential Input Voltage 0.3V (min) -(max)

Can you teach how to read their comon mode ranges and diff swings are same so they are identical?

Thanks.

-qlyus

qlyus, I don't know, but I suspect that this is the case:-

1) The differential receivers works over a very large common mode range. The common mode voltage probably affects the switching speed though. 2) The receivers work with very small differential voltages, with the gotcha being that the smaller the differential voltage the slower the switching. 3) Xilinx only test the parts to the specifications you quote, because they can't, or it's too expensive to, check all inputs over all common mode voltages and differential voltages meet all timing for every part off the production line.

So, it's physically the *same* receiver, it's just only tested at the two LVPECL (and the LVDS I guess) points you quote. Good luck, Symsx.