Why does Synplify add clock buffers?

I have an Actel design with a 3 clocks. I need to define two of them in Synplify (v8.5):

define_clock -name {n:clk2} -freq 20 define_clock -name {n:clk1} -freq 100

This will make Synplify to insert clock buffers in the design:

clk2_keep : CLKINT port map(A => clk2_i, Y => clk2);

The problem is that the Actel PAR tool "Designer" (v7.1) doesn't like these buffers as it will assign the clocks to global clock networks anyway:

Error: CMP601: This design has a CLKINT instance 'clk2_keep' driven by a clock net which is not needed. Before compiling this design, this macro must be removed from the design.

How do i get rid of them? I tried to fix this by setting the max fanout to a very high value: define_attribute {n:clk1} syn_maxfan {200000} define_attribute {n:clk2} syn_maxfan {200000}

but it didnt work :(

Designer has an option for removing unsued buffers, but I never get to the optimization stage. Any suggestions how i can stop Synplify from inserting clock buffers or get Designer to ignore the buffer?

regards, - Burns

PS. here are the rest of the constraints

forward annotated from Synplify to Designer (as SDC constraints): create_clock -period 50 -waveform {0.000000 25.00000} clk2 create_clock -period 10 -waveform {0.000000 5.00000} clk1

additional PDC constraints imported to Designer: assign_global_clock -net {clk2} assign_global_clock -net {clk1}