Thank you mk for your reply.
I pasted here the failed annotations, SDF file and verilog model. What shall I do now with this kind of failures?
Thank you.
Here are the failed annotations.
--------------- ncverilog: v03.40.(s004): (c) Copyright 1995 - 2002 Cadence Design Systems, Inc. ncverilog: v03.40.(s004): Started on Nov 12, 2004 at 17:59:04 ncverilog +access+r -f sim ../../synthesis/netlist/sdm_wlan_net.v ./sdm_top_tbg.v ./include_lib.v .............................. ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check (RECOVERY (posedge CL) (posedge CK) (64.11)) of instance tsdg.sdm_wlan.\r_sumout4_reg[2] of module SCJFD21S20. ncelab: * W,SDFNET: Failed Attempt to annotate to non-existent timing check (SETUP (posedge D) (posedge CK) (188.037)) of instance tsdg.sdm_wlan.\r_sumout4_reg[2] of module SCJFD21S20. ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check (SETUP (negedge D) (posedge CK) (187.369)) of instance tsdg.sdm_wlan.\r_sumout4_reg[2] of module SCJFD21S20. ncelab: * W,SDFNET: Failed Attempt to annotate to non-existent timing check (HOLD (posedge D) (posedge CK) (114.384)) of instance tsdg.sdm_wlan.\r_sumout4_reg[2] of module SCJFD21S20. ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check (HOLD (negedge D) (posedge CK) (114.766)) of instance tsdg.sdm_wlan.\r_sumout4_reg[2] of module SCJFD21S20.
Here is the SDF segment.
--------------- (DELAYFILE (SDFVERSION "OVI 2.1") (DESIGN "sdm_wlan") (DATE "Fri Nov 12 14:28:19 2004") (VENDOR "cs91sn_uc_core_worst_max") (PROGRAM "Synopsys Design Compiler cmos") (VERSION "2001.08") (DIVIDER /) (VOLTAGE 1.10:1.10:1.10) (PROCESS "DEFAULT") (TEMPERATURE 125.00:125.00:125.00) (TIMESCALE 1ps) ........ (CELL (CELLTYPE "SCJFD21S20") (INSTANCE r_sumout4_reg\[2\]) (DELAY (ABSOLUTE (IOPATH CK Q (364.590:364.590:364.590) (349.149:349.149:349.149)) (IOPATH CL Q (0.000:0.000:0.000) (132.917:132.917:132.917)) ) ) (TIMINGCHECK (WIDTH (posedge CK) (231.800:231.800:231.800)) (WIDTH (negedge CK) (269.800:269.800:269.800)) (RECOVERY (posedge CL) (posedge CK) (64.110:64.110:64.110)) (HOLD (posedge CL) (posedge CK) (233.606:233.606:233.606)) (SETUP (posedge D) (posedge CK) (188.036:188.037:188.037)) (SETUP (negedge D) (posedge CK) (187.369:187.369:187.369)) (HOLD (posedge D) (posedge CK) (114.385:114.384:114.384)) (HOLD (negedge D) (posedge CK) (114.766:114.766:114.766)) (WIDTH (negedge CL) (212.800:212.800:212.800)) ) )
And here is the cell verilog mode.
------------------ `resetall `timescale 1ps/1ps `celldefine `ifdef verifault `suppress_faults `enable_portfaults `endif `ifdef FAST_FUNC `delay_mode_unit `else `delay_mode_path `endif module SCJFD21S10( Q, CL, D, CK ); input CL, D, CK; output Q; reg notifier ; supply1 clip_1 ; `ifdef FAST_FUNC `ifdef cwave UDP_DFFQ I_00p01( N_00, CK_fjcw, D_fjcw, CL_fjcw, clip_1, notifier); buf #1 ( Q, N_00); buf ( CL_fjcw, CL); buf ( D_fjcw, D); buf ( CK_fjcw, CK); `else UDP_DFFQ I_00p01( N_00, CK, D, CL, clip_1, notifier); buf #1 ( Q, N_00); `endif
`else `ifdef cwave UDP_DFFQ I_00p01( N_00, CK_fjcw, D_fjcw, CL_fjcw, clip_1, notifier); buf ( Q, N_00); buf ( CL_fjcw, CL); buf ( D_fjcw, D); buf ( CK_fjcw, CK); `else UDP_DFFQ I_00p01( N_00, CK, D, CL, clip_1, notifier); buf ( Q, N_00); `endif
// TIMING CHECK NETLIST // SDF format V2.1 UDP_EE1 ( CLe1, CL, clip_1); UDP_EE0 ( CKe0, CK, clip_1); and ( CLe1andDn0, CLe1, Dn0); UDP_NE0 ( Dn0, D, clip_1);
specify // PATH DELAY (CL +=> Q) = (0 : 0 : 0 , 36.8 : 61.4 : 101.3); (CK => Q) = (107.0 : 178.4 : 294.4 , 106.8 : 178.1 : 293.8); `ifdef no_ifnone `else `endif
`ifdef bus_con_float_check `ifdef dcmos specparam BUSCHECK$ = 0; `else specparam BUSCHECK$ = 0; `endif `else `ifdef dcmos specparam BUSCHECK$ = 0; `endif `endif `ifdef finfo specparam AREA$ = 198.000000, BC$ = 7.000000, ILF$CL = 0.00364, ILF$D = 0.00166, ILF$CK = 0.00228; `endif // Timing Checks specparam TCLW1_CL_CL = 67.20 : 112.00 : 184.80 , TCKWH2_CK_CK = 65.40 : 109.00 : 179.85 , TCKWL3_CK_CK = 85.80 : 143.00 : 235.95 , TSCL4_CL_CK = 262.35 : 437.26 : 721.47 , THCL5_CK_CL = 221.11 : 368.52 : 608.05 , TSD6_D_CK = 117.13 : 195.22 : 322.11 , THD7_CK_D = 86.10 : 143.50 : 236.77 ; $width( negedge CL , TCLW1_CL_CL , 0 , notifier ); $width( posedge CK &&& CLe1 , TCKWH2_CK_CK , 0 , notifier ); $width( negedge CK &&& CLe1 , TCKWL3_CK_CK , 0 , notifier ); // SDF format V2.1 `ifdef sigstm $setup( posedge CL &&& CKe0 , posedge CK &&& CLe1andDn0 , TSCL4_CL_CK , notifier ); $hold( posedge CK &&& Dn0 , posedge CL , THCL5_CK_CL , notifier ); $setup( posedge D &&& CKe0 , posedge CK &&& CLe1 , TSD6_D_CK , notifier ); $setup( negedge D &&& CKe0 , posedge CK &&& CLe1 , TSD6_D_CK , notifier ); $hold( posedge CK &&& CLe1 , posedge D &&& CLe1 , THD7_CK_D , notifier ); $hold( posedge CK &&& CLe1 , negedge D &&& CLe1 , THD7_CK_D , notifier ); `else `ifdef pre_sdf $recovery( posedge CL &&& CKe0 , posedge CK &&& CLe1andDn0 , TSCL4_CL_CK , notifier ); $hold( posedge CK &&& Dn0 , posedge CL , THCL5_CK_CL , notifier ); $setup( posedge D &&& CKe0 , posedge CK &&& CLe1 , TSD6_D_CK , notifier ); $setup( negedge D &&& CKe0 , posedge CK &&& CLe1 , TSD6_D_CK , notifier ); $hold( posedge CK &&& CLe1 , posedge D &&& CLe1 , THD7_CK_D , notifier ); $hold( posedge CK &&& CLe1 , negedge D &&& CLe1 , THD7_CK_D , notifier ); `else $setup( posedge CL &&& CKe0 , posedge CK &&& CLe1andDn0 , TSCL4_CL_CK , notifier ); $hold( posedge CK &&& Dn0 , posedge CL , THCL5_CK_CL , notifier ); $setup( D &&& CKe0 , posedge CK &&& CLe1 , TSD6_D_CK , notifier ); $hold( posedge CK &&& CLe1 , D &&& CLe1 , THD7_CK_D , notifier ); `endif
`endif endspecify `endif // end of FAST_FUNC endmodule
"mk" wrote in message news: snipped-for-privacy@4ax.com...
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