1. Home
  2. Field-Programmable Gate Arrays
  3. Why does a 36 x 36 Multiplier in a Xilinx Spartan 3E require 9 multipliers?

Why does a 36 x 36 Multiplier in a Xilinx Spartan 3E require 9 multipliers?

I'm implementing a 36 bit x 36 bit multiplier with a 72 bit output in a Xilinx Spartan 3E. I've tried to poke down into the RTL schematic, but I'm unable to push down into the multiplier block.

Could you please explain architecturally why this requires 9 multipliers?

Thanks, Dale

Reply to
Dale
Loading thread data ...

Just a guess, but I imagine the multipliers are signed 18x18, so you can't use all 18 bits when you try to extend them?

Reply to
Gabor

You can do a 35x35 multiplier with four DSP48s, but doing a 36x36 takes more because you can't use the 18th (sign) bit in the LSB DSP48s. See fig 1-21 of this doc:

formatting link
(This is for V4 designs but I think the concept is the same.) I don't know what you used to design this and why you can't look inside the RTL schematic, but maybe you can try the technology schematic.

-Kevin

Reply to
Kevin Neilson

Thanks for the comments. That was correct. Because it's a signed multiply in blocks of 18x18 it reduces the throughput of each input by one bit. I implemented a 35 x 35 multiplier and it only used 4 multipliers as I would expect.

Thanks again, Dale

Reply to
Dale

You only need two adders to extend a 35x35 to 36x36. Maybe you cann use the final adders in the DSP slice for that.

Kolja Sulimma

Reply to
comp.arch.fpga

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.