Hi Group, Iam not sure if this is the right group to post my query on,butI would appreciate any kind of information.I am relatively new to VHDL and am tring to understand whyVHDL gate level descriptions simulate slower than verilog models.I was told that it was because how the VHDL model gets evaluated (delay models) that makes it slower.I didnt quite follow this and if somebody in the group could point me towards a more detailed explanation ,it would be great.I would also like to know why do we see better VHDL performace at behavioural descriptions(as compared to verilog behavioural descriptions.).I am sorry if this has been discussed previously.
Thanks, Abilash.