why do i see negative clock hold time

hello when i look at the timing report of my fpga i see that the why do i see negative clock hold time of my input pins is NEGATIVE Thold= -5ns

i dont understand why

thanks for the help

Reply to
guy
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I assume you mean a negative data hold time (with respect to the clock). This is caused by having a much greater delay in the pad to D input of a flip flop than in the pad to clock input. Having combinatorial logic between the pad and the flip flop could be one cause. Presumably your setup time requirement is rather lengthy too.

Reply to
David Spencer

Thold is the amount of time after the clock that the input must remain stable. Negative hold time means that the input does not need to be stable for some period of time prior to the clock.

If the Thold= -5ns that you're looking at is for the fast timing model, it means that you could theoretically switch the input 5 ns prior to the clock and it would still work.

If the Thold is in a report from the slow timing model, then the number is meaningless.

KJ

Reply to
KJ

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