Which programmable clock for Spartan3 starter board and A/D-converter

You can use the Digital Clock Manager (DCM) to adjust duty-cycle, phase and frequency with the 50MHz GCLK0 input you have.

I like point to point routing where possible. You may be able to use a clock forwarding scheme (via an FDDRCPE instance) to achieve this. There are also board deskewing schemes via feedback that may be suitable. I think the feedback scheme necessitates a 'T' in the board routing.

Must is a strong word without an estimate of the power saving that are achievable by doing this. I think the MicroBlaze people want to do this, but are worried about handling/preventing transition glitches. I don't have the details off the top of my head.

JTAG typically uses the TCLK. CCLK is either an input or output clock depending on the configuration mode selected.

Hope this helps.

- Newman

Hi again!

Yeah, but doesn't this cause delays by routing this to an output-port for driving the A/D?

I'm stupid (or maybe I just haven't learned all this stuff yet) so please explain all these terms like "point to point routing", "clock forwarding scheme" and what do you mean by a "board deskewing schemes via feedback" and what is a 'T'?

Thanks, Preben

It depends on your timing budget. There is a thing called a DLL that phase locks the clock input to the destination synchronous clock input. It can also double the frequency. It has the ability to adjust the phase of the clock to null out the estimated first order delay of the IOB (note use of FDDRCPE) and PCB transport delay. If more precision is needed for temperature / voltage compensation, then maybe the feedback approach is better.

I think my explanation was inadequate. What I meant by point to point is that there are only two component connection involved in routing the trace on the PCB (There may also be a series source termination resistor in the path). I believe that the feedback scheme wants a minimum of three component connections. One from the FPGA output pin to the destination, and an equal length path from the FPGA output pin to the FPGA feedback pin.

I've never used the feedback method, but I suspect that I would research "Source Termination of Multiple Clock Lines" section 11.5 "High-Speed Digital Design A Handbook Of Black Magic" by Howard Johnson and Martin Graham where there is a short segment from the output clock pin to two series resistors (what I called the "T") to two lines of equal length and the loads at each end are balanced.

Hope this helps, Newman

P.S. I've seen this book at my local Barnes and Nobles. It may be available close to you too.

I have used the DLL's but the FDDRCPE is not something I know anything about?

the feedback approach is

How do I make the feedback approach out of the IC?

Do I just send out the clock to the IO-pin and then back to some other IO-pin after having been "around" the A/D? Or any special pins for this purpose?

Which means that I should add a "clock-line" on the PCB from the output-pin to the A/D. And from the same output just "draw" a line exactly as long as the line to the A/D, but know to a pin on the FPGA (feedback)?

How should the clock be terminated on the board-layout (I must say - i never made a PCB design - this will be my first - sounds silly, but we are educated using already made development boards)

I somehow don't see how these attempts make sure that the outside clock is different from the same signal just inside the IC. I guess that somehow you will need two clock-lines (one to the internal and one for the external).

If you have time for making a simple "point-to-point" example of the clock-net circuit (on the board that I should produce), please feel free to do so. I haven't got much time up to christmas and I'm very new to this High speed era of electronics, and somehow my bachelor starts tomorrow, so the PCB should be finished quite soon so I can start on my project.

Thanks (but the money as a student is very small, so maybe the library can be used - i'll try so)..

Thanks for all your help, and very sorry about my very bad english!

/ Preben

I did a quick search at

keyword clock forward There are a lot of hits. I think you would be better off reading thru them.

I did a quick search at

keyword dcm feedback I got this link. There are a lot of hits. I think you would be better off reading thru them.

I believe there are timing optimized feedback pins that you use. Please search Xilinx web for specifics.

You are in a sense lucky that you get a crack at fabbing a board while in school. It was a long time before I got involved with PCB's. After you are out of school for a while, people expect success even if you have not done something like it before. I no longer do PCB's, essentially because I have been able to get away with just doing the internals of the FPGA's :)

I think it is better that you read the Xilinx app-notes on the subject rather than rely on my memory about them.

There are a lot of issues like decoupling, via hole size, cross talk, PCB layer stack-up, board impedence, trace width, describing critical routes, etc. People claim that board simulation should be done with IBIS models, with back-annotated board parasitics nowadays. I do not have access to such tools, and feel reluctant to give you advice in this area. I had good success doing PCB's, but it was perhaps due to making the PCB very simple to place and route. I don't know what type of A/D you are using, but care should be used to keep the area "quiet" if you expect the LSB weights of the digitized outputs not to be flapping in the breeze "e.g. toggling with a DC signal as a reference". You really need to read the A/D applications notes to get a handle on this.

My take on the clock is to convince yourself that the FDDRCPE approach will do the job. If so inclined, layout the board using the feedback approach with a series resistor in each clock leg as close to the source as possible. Make it symetrical, and if you have problems, you can depopulate the feedback resistor, and use the FDDRCPE approach. The trace stub to the depopulated resistor should be very short to minimize reflections. Maybe it will work. A back annotated board simulation would be nice for a confidence builder, but I am not the one to give advice on the particulars.

My response on the above is guarded, because I have never seen what I just described as a recommended practice in any Xilinx document.

The formula for the source-termination resistors is Rs = Zo - Rdrive*N Where : Rs = source termination resistor Zo = driven line impedence Rdrive = effective output resistance of driver N = number of driven lines

Your English is pretty good!

Good-Luck,

-Newman