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which commercial HDL-Simulator for FPGA?

As commodity PC hardware and prouctivity applications deline in price, EDA tools are as (relatively) expensive as ever, necessitating yet another discussion of "Which simulator is right for me?"

The contendors are ...

1) Aldec Active-HDL + great design-flow assistants (state-diagram, block-diagram, waveform-diagram editing, export to PDF) + possibly faster than Modelsim/PE? - no direct support in FPGA design-suites (Webpack/Quartus) - Windoze only (can WINE 1.0 run it?) - Systemverilog is almost but not quite usable ('package' not supported?!?) "less than $6000 for mixed-lang. VHDL+Verilog simulation" (Note, that configuration is the most basic, doesn't have SWIFT/Smartmodel) [first year pepetual-license, yearly maint. is additional 20%/year]

2) Mentor Modelsim PE + currently more solid Systemverilog support than Active-HDL, (but limited to design-constructs, no assertions/coverage) + de-facto industry standard, direct integration into FPGA design-suites (Webpack/Quartus) + SWIFT/Smartmodel support (no extra cost if using mixed-HDL license) - I really don't like the integrated waveform viewer - Windoze only (can WINE 1.0 run it?) "less than $10,000 for mixed-lang. VHDL+Verilog simulation" [first year perpetual-license, yearly maint. is additional 20%/year]

3) FPGA-vendor OEM solution (usually a crippled Modelsim/PE) + cheapest + Altera Modelsim officially supports Linux (Xilinx does not) + Xilinx Modelsim has same level of (design construct) Systemverilog support as Modelsim/PE, quite good actually - limited capacity, deliberately slower runtime performance - term-based only (no perpetual license for Xilinx/Altera?) - no mixed-HDL (VHDL+Verilog) -- deal-killer for me... "less than $1500 for 1-language, 1-year license"

If I only had to do 'abstract' RTL-design (algorithm proof, no device-dependent instantiations...)

*4) gHDL, Icarus Verilog + free, open-source VHDL, Verilog - emacs/gvim not included - no mixed-HDL (VHDL+Verilog) sim

.............

Kidding aside, my real requirements:

1) I foresee mixed-HDL as a *requirement* for any serious consulting job. (Xilinx and Altera are pretty good about providing 'HDL-neutral IP', but third-parties aren't.)

2) ASIC sign-off is obviously not a concern -- who's going to compete with a professional turn-key bureau?

3) Design-size (capacity) is an unknown. For front-end (RTL) simulation, I think even the OEM Modelsims are adequate. But for gate-level, that might push them over the limit. It's interesting that even a 'budget'
Reply to
SynopsysFPGAexpress
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This reads like a thinly veiled marketing survey.

If you actually are a designer, get a proto design ready, order evals of each simulator then try them and see for yourself.

Which part were you kidding about?

The device vendors are only HDL-neutral because they are selling device netlists, not source code. Not a plus in my book.

-- Mike Treseler

Reply to
Mike Treseler

Don't forget

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I personally like Finsim (from Fintronic) a lot. It's a compiled simulator and it's quite fast.

Reply to
Muzaffer Kal

Both appear to fail the OP's requirements (and mine); they look to be Verilog only.

- Brian

Reply to
Brian Drummond

forget

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I've been using Veritak, a low cost Veritak simulator. It has had some bugs, but the author is VERY quick to fix problems. A surprise - he is also VERY responsive to requests for new features or enhancements. I'm very pleased with his product.

John Providenza

Reply to
jprovidenza

...

If you have Xilinx ISE 10.1, check out ISIM, which comes "free" with it. It's much improved and may meet your needs and in future releases should have better a better user interface. I don't think it currently supports SystemVerilog, (and you are correct in propagating your religion) but might soon. Modelsim is still the best, but you pay for a lot of things you don't really need, and the waveform viewer could be improved. That's where you spend 90% of your time during debugging so it should be a little easier to use.

-Kevin

Reply to
Kevin Neilson

I've used vcs and currently have access to ncsim, so I've not bothered with modelsim. However, recently I tried the free one which comes with Altera web edition.

So in either of these, you typically simulate and have all signals dumped to a huge output file (using $dumpvars(0); $dumpon; for vcs or $shm_open(...); $shm_probe(..); for ncsim). Then you can explore the design hierarchy and choose which signals to view in vcs -RPP or simvision. The same is true for even icarus verilog with gtkwave.

However with modelsim it looks like there is no way to do this. Instead, when you add a signal to the viewer in the GUI, it re-runs the entire simulation to get the new signal. Am I missing something or is this really how it works? I can't believe that it would really work this way.

(Also the crippled free modelsim is slower than icarus).

Has anyone tried to simulate Altera's IP with icarus? I'm thinking about the .vo simulation model of the altmemphy DDR controller.

--
/*  jhallen@world.std.com AB1GO */                        /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Reply to
Joseph H Allen

Invoke vsim with -do "log -r *; run -all; quit -f" and -wlf "mydump.wlf", and you'll get similar results (just in a different format). In my experience ncsim is faster than Modelsim, and of course it carries a higher price tag.

Older versions of Modelsim also seems to stall after long simulations, wehreas ncsim never gave me any problems.

--
Faster, faster, you fool, you fool!
		-- Bill Cosby
Reply to
Jason Zheng

This didn't work, but I eventually figured it out:

Start with an empty directory except for some verilog files you want to simulate:

# Create work directory vlib work

# Compile verilog files (vcom for vhdl) vlog tb.v vlog dut.v

# Simulate vsim -do "log -r *; run -all; quit -f" work.tb

- this creates a vsim.wlf file with everything in it just as you say.

Now try to view the waveform. If I try:

vsim -wlf vsim.wlf work.tb -do "view wave; add wave *"

This brings up modelsim GUI and opens the waveform viewer window. All of signals are in the viewer, and they're all empty.

But this does work:

vsim -view vsim.wlf -do "view wave; add wave *"

but it won't work after you have done the previous vsim -wlf command, vsim

-wlf does something to the .wlf file or sets something in an initialization file somewhere. I had to re-run the simulation before "vsim -view ..." for it to work.

BTW, I notice that if I do add

initial begin $dumpvars(0); $dumpon; ... end

vsim will generate a dump.vcd file, and I can use gtkwave to view it just fine. I had thought this didn't work, I guess I was wrong or something changed recently. Maybe I should just forget about using modelsim's built-in viewer.

I notice that when the GUI is open, I can't also run a simulation on the command line because there is only one license.

This is modelsim 6.1g which comes with Quartus 8.0 web edition running under windows.

--
/*  jhallen@world.std.com AB1GO */                        /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Reply to
Joseph H Allen

One vote for Active-HDL. I briefly used Modelsim before we bought Active-HDL and for me anyway, the Active-HDL interface is much better. It's true that it's not officially supported by Xilinx but in practice that really never caused too much of a problem.

I really like to create a schematic top level with blocks that are either more schematics themselves or directly vhdl blocks. That way it's much easier to see how everything connects together, it helps comprehension. I don't quite understand why some people insist on writing direct VHDL connections between blocks. It's a little bit like insisting on writing pspice netlists for simulations instead of using the schematic editor. Active-HDL converts schematics to vhdl code anyway, so it's never too late to go back to vhdl-only code. The resulting code will be very clean if you keep your top level free of logic.

The state-machine editor in Active-HDL is another story. To me simple state machines don't need to be represented by a diagram to be understood. On the other hand, large ones are hard to represent in a diagram. So in the end I only write vhdl state machines.

Patrick

Reply to
Patrick Dubois

It is, I apologize if I mislead anyone. I wanted to hear other people's choices and compare them to my situation.

For gHDL and Icarus Verilog, I said "emacs/gvim not included." It was a poor attempt at humor.

That's something I didn't think about, and I checked Xilinx's website. It turns out, some of their IP-blocks (Microblaze, PCIe, PPC440, etc.) use a new 'SecureIP' format, and so far, only Modelsim is supported. That doesn't bode well, either...

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Reply to
SynopsysFPGAexpress

Apologies if you are a Xilinx person, but I tried their Web Pack edition with the in house tools and the simulator really sucks... or blows or something not so good. Although I didn't see any issues with the simulation speed, the compile speed is pretty slow. I was using it for a while when my design was pretty small and the compiles were taking half a minute. Using Aldec Active HDL the compiles take a second for a much larger design and the simulation speed is not bad considering that it is "crippled"ware.

Xilinx seems committed to improving their in house sim. I posted about in a news group and got a reply from one of the developers which was almost apologetic and sincerely interested in what I found lacking.

In the meantime I expect to stick with commercial packages. When I do make the switch, it will likely be to an open source simulator.

Rick

Reply to
rickman

I use a purely HDL hierarchy. I find that top level schematics or even low level schematics of large functions tend to end up being more like a net list than a drawing anyway. You have pins with names X,Y,Z connected to net R,S,T on page 1. On page 2 you have nets R,S,T connected to another part with pin names A,B,C. Making it a drawing doesn't add much in my opinion. Once I gave up hope for schematics and embraced the HDL world, I found joy in a life of text files and the infinite advantages they have in the land of version control!

I agree. Again a diagram can only offer a bit more here than can the HDL text file, but I don't like using special tools that make the code more difficult to port. Keeping it in HDL can work well and has all of those text and portability advantages.

Rick

Reply to
rickman

I've done some benchmarking on Verilog simulators. Here are the times for running our regression suite on one of our cores. I ran the test suite on Cadence NCSim on CentOS5, Mentor's Questa on both CentOS5 and XP, and Altera's Modelsim on CentOS5. The system is a 3GHz Core2 with 8G of DDR. NC is the fastest but Questa on CentOS5 is close. Questa on XP is much slower then it is on Linux. The Altera ModelSim is dog slow which is to be expected, I'm sure that Mentor has deliberately crippled it.

NC, Linux 0:06:34 Questa, Linux 0:07:15 Questa, XP 0:18:14 Altera ModelSim, Linux 1:00:13

Reply to
General Schvantzkopf

Lies, damn lies and benchmarks :-)

Benchmarking is very difficult and not only requires multiple designs and knowing the environment inside out you also need to know what the simulator is doing to your code. Verilog has the advantage(?) that you can tweak the simulator to improve performance however, this might break some simulations. (Un)fortunately this is not possible with VHDL which is far more stricter in what you can do with the compiler. Using one core without mentioning how you measured it, simulator/compiler settings, versions etc is not much use IMHO.

I found the same.

This is fully documented. I believe the OEM versions are about 40% of PE, however, the problem is that after a certain number of lines it grinds to a halt and becomes completely useless.

Hans

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Reply to
HT-Lab

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The "-wlf XXXX.wlf" option renames the output file to 'XXXX.wlf'. So if you run your sim and then run the command with the -view option, it'll work fine. If you run 'vsim -wlf vsim.wlf work.tb -do "view wave; add wave *"', it erases your previous vsim.wlf and opens a new one with that name. That's why the waveform opens with no data.

I'll typically add the signals I want to log to a .do file instead of logging all of the signals in a design. The more signals you log, the slower ModelSIM runs.

Yea, but if you have the GUI open already, why not just run the sim in the GUI?

Reply to
kkoorndyk

I agree that a top level schematic is exactly like a netlist, but the difference to me anyway is that I can quickly grasp how each blocks are connected together. I try to keep most blocks on one large 11x17 page. Here's an example of what I mean:

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With a netlist, I have to read the several lines of vhdl code to understand how the blocks are connected and that takes a longer time. Ideally, the vhdl netlist is also accompanied by a block diagram. With the schematics flow, the block diagram comes free.

The drawbacks of course are the version control problems associated with schematics files and the lack of a standard file format. To me the version control issues are not a big deal because all the meat is in the vhdl blocks anyway, not the top level.

Patrick

Reply to
Patrick Dubois

Thanks for taking the time to run the test and for sharing the results. Interesting that speed is roughly proportional to the cost of the license.

While the oem version is "dog slow" in this lineup, it is still quite useful for debugging rtl when all the licenses are checked out.

-- Mike Treseler

Reply to
Mike Treseler

What should be of most interest to anyone who is looking to buy a serious simulator is the difference between Linux and XP. I ran the same version of Questa on both Linux and XP with the same license. Questa runs three times as fast on Linux as it does on XP. I'm pretty sure that the time difference can be attributed to the performance of the Linux file system (EXT3) vs the XP file system (NTFS). The real purpose of my investigation was to compare various Virtualization tools. I gathered the numbers that I posted before on the native OSes to give me a baseline. I then ran the NC and Questa tests on VMware Server, VMware Workstation and KVM. When using a virtual disk all of the VMs were only 5-10% slower then native, KVM being the fastest. However if I used a host machine directory that was accessed via NFS the performance dropped dramatically, about 2.5X for VMware and 5X for KVM. VMware's shared folders were just as fast as VMware's virtual disk performance i.e. about 10% slower then the native performance. The NFS mounted host directory performance on VMware was about the same as native XP performance which leads me to believe that XP's problem is it's file system.

Reply to
General Schvantzkopf

It would be interesting to see Icarus in this list. Also Verilator...

--
/*  jhallen@world.std.com AB1GO */                        /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Reply to
Joseph H Allen

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