Hi, I am learning a simple 16 bits adder using VHDL:
begin a1: process (CLK) variable count_a, count_b : std_logic_vector(15 downto 0); begin if (CLK'event and CLK = '1') then count_a := A; count_b := B; CLK
LUT2, MUXCY and XORCY are inside the slice.
Using fpga_editor, double click on one of the used slices. Each slice contains two LUT2, two MUXCY and two XORCY.
MUXCY is part of the carry chain and is on the centerline of the diagram. XORCY is drawn as an XOR gate, so you should be able to find it.
The MUXCY are named CYMUXF and CYMUXG. The XORCY are named XORF and XORG.
Alan Nishioka
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