Where is the logic?

The following code:

module PROBLEM ( input wire CLK, input wire [9:0] A, input wire [9:0] B, output reg [9:0] OUT ); wire [9:0] xor2; XOR2 XOR2_0 (.O(xor2[0]), .I0(A[0]), .I1(B[0])); XOR2 XOR2_1 (.O(xor2[1]), .I0(A[1]), .I1(B[1])); XOR2 XOR2_2 (.O(xor2[2]), .I0(A[2]), .I1(B[2])); XOR2 XOR2_3 (.O(xor2[3]), .I0(A[3]), .I1(B[3])); XOR2 XOR2_4 (.O(xor2[4]), .I0(A[4]), .I1(B[4])); XOR2 XOR2_5 (.O(xor2[5]), .I0(A[5]), .I1(B[5])); XOR2 XOR2_6 (.O(xor2[6]), .I0(A[6]), .I1(B[6])); XOR2 XOR2_7 (.O(xor2[7]), .I0(A[7]), .I1(B[7])); XOR2 XOR2_8 (.O(xor2[8]), .I0(A[8]), .I1(B[8])); XOR2 XOR2_9 (.O(xor2[9]), .I0(A[9]), .I1(B[9]));

always @(posedge CLK) OUT

Reply to
Martin Euredjian
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You say the LUTs are not there. How about the registers?

You might want to open a case for this with Xilinx. It can be an uphill battle trying to get them to understand what you are doing and why. But certainly the problem itself is not difficult to convey.

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Rick "rickman" Collins

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rickman

Sorry, I should have mentioned that, yes, the registers are there. Floorplanner shows no input to the registers at all, just the output rubberbanding to the corresponding IOB. FPGA Editor shows all logic connected per the HDL description.

The bummer here is that I'm trying to create some pretty complex RPM's and Floorplanner is a nice way to see how things are laying out. Unless someone tells me that I'm missing something in my sample code, I guess I'll have to use FPGA Editor.

They've been pretty good to me in the past...but, then again, I've only put in a couple or so simple cases. I'll typically get myself to the point of absolute frustration before either posting on the newsgroup or seeking other help (like using the Force, which should not be done lightly). :-)

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Martin Euredjian
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Martin Euredjian

I wonder if using FMAP might make a difference here? The trouble is... I couldn't figure out how to define a simple two-input XOR gate from both the Libraries Guide and Constraints Guide (MAP) entries. Can anyone point me to detailed documentation on the subject?

Thanks,

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Martin Euredjian
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Martin Euredjian

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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

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Reply to
Ray Andraka

Hi Martin, The floorplanner only shows logic that can be floorplanned. The problem is the use of the XOR2 which is a primitive element in the Xilinx Library. This XOR2 element can not be constrained in the UCF file because it is not a LUT it is just logic. If the XOR2 gate was not instantiated then XST would generate a LUT which could be constrained and viewed in the floorplanner. After the map phase it is mapped to a LUT (thus why you see it in the fpga editor), but this is too late to add constraints to.

If you add a new definition for the XOR2 to your design, I believe this will fix your problem. You may eventually want to change the name of the XOR2 module in order to avoid confusion with the library primitive.

module XOR2 ( output O, input I0, input I1 )/* synthesis attribute lut_map of XOR2 is yes*/; assign O = I0 ^ I1; endmodule // XOR2

- Tom Branca

- Xilinx

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Tom Branca

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"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

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Ray Andraka

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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com
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"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

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Ray Andraka

ISE6.1i / XST

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Martin Euredjian
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Martin Euredjian

That's correct. The LUT's are not showing up at all, anywhere, graphically or otherwise. I just doubled checked that. The Design Hierahchy window shows the IOB's, CLK, DFF's and that's it.

Being that it's so short I'll type the contents of the Design Hierarchy window below:

PROBLEM "PROBLEM" [31 IOBs, 10 DFFs, 1 BUFG] |_ CLK_BUFGP [BUFGP] O:CLK_BUFGP I:CLK |_ OUT_9 [DFF] Q:OUT_9 D:xor2 C:CLK_BUFGP |_ OUT_8 [DFF] Q:OUT_8 D:xor2 C:CLK_BUFGP |_ OUT_7 [DFF] Q:OUT_7 D:xor2 C:CLK_BUFGP |_ OUT_6 [DFF] Q:OUT_6 D:xor2 C:CLK_BUFGP |_ OUT_5 [DFF] Q:OUT_5 D:xor2 C:CLK_BUFGP |_ OUT_4 [DFF] Q:OUT_4 D:xor2 C:CLK_BUFGP |_ OUT_3 [DFF] Q:OUT_3 D:xor2 C:CLK_BUFGP |_ OUT_2 [DFF] Q:OUT_2 D:xor2 C:CLK_BUFGP |_ OUT_1 [DFF] Q:OUT_1 D:xor2 C:CLK_BUFGP |_ OUT_0 [DFF] Q:OUT_0 D:xor2 C:CLK_BUFGP |_ OUT [IOB] O1:xor2 OTCLK1:CLK_BUFGP ... weird! |_ OUT [IOB] O1:xor2 OTCLK1:CLK_BUFGP ... |_ OUT [IOB] O1:xor2 OTCLK1:CLK_BUFGP ... |_ OUT [IOB] O1:xor2 OTCLK1:CLK_BUFGP ... |_ OUT [IOB] O1:xor2 OTCLK1:CLK_BUFGP ... |_ OUT [IOB] O1:xor2 OTCLK1:CLK_BUFGP ... |_ OUT [IOB] O1:xor2 OTCLK1:CLK_BUFGP ... |_ OUT [IOB] O1:xor2 OTCLK1:CLK_BUFGP ... |_ OUT [IOB] O1:xor2 OTCLK1:CLK_BUFGP ... |_ OUT [IOB] O1:xor2 OTCLK1:CLK_BUFGP ... |_ CLK [IOB] I:CLK_BUFGP/IBUFG |_ B [IOB]I:B_9_IBUF |_ B [IOB]I:B_8_IBUF |_ B [IOB]I:B_7_IBUF |_ B [IOB]I:B_6_IBUF |_ B [IOB]I:B_5_IBUF |_ B [IOB]I:B_4_IBUF |_ B [IOB]I:B_3_IBUF |_ B [IOB]I:B_2_IBUF |_ B [IOB]I:B_1_IBUF |_ B [IOB]I:B_0_IBUF |_ A [IOB]I:A_9_IBUF |_ A [IOB]I:A_8_IBUF |_ A [IOB]I:A_7_IBUF |_ A [IOB]I:A_6_IBUF |_ A [IOB]I:A_5_IBUF |_ A [IOB]I:A_4_IBUF |_ A [IOB]I:A_3_IBUF |_ A [IOB]I:A_2_IBUF |_ A [IOB]I:A_1_IBUF |_ A [IOB]I:A_0_IBUF

This is what's in the FPGA Editor's "List 1" window when set to "All Components":

Name Site Type #Pins Hilited A C12 IOB 1 15 A C10 IOB 1 15 A E11 IOB 1 15 A B13 IOB 1 15 A C11 IOB 1 15 A F10 IOB 1 15 A A7 IOB 1 15 A K21 IOB 1 15 A E15 IOB 1 15 A L5 IOB 1 15 B A13 IOB 1 15 B B10 IOB 1 15 B D10 IOB 1 15 B A11 IOB 1 15 B D11 IOB 1 15 B F12 IOB 1 15 B B7 IOB 1 15 B K22 IOB 1 15 B B16 IOB 1 15 B L4 IOB 1 15 CLK D12 IOB 1 15 CLK_BUFGP/BUFG BUFGMUX0S BUFGMUX 3 15 OUT B12 IOB 2 15 OUT F11 IOB 2 15 OUT E12 IOB 2 15 OUT B11 IOB 2 15 OUT F13 IOB 2 15 OUT A10 IOB 2 15 OUT A8 IOB 2 15 OUT K20 IOB 2 15 OUT F14 IOB 2 15 OUT C8 IOB 2 15 PWR_VCC_0 VCC_X19Y1 VCC 1 15 xor2 SLICE_X34Y78 SLICE 3 15 xor2 SLICE_X26Y79 SLICE 3 15 xor2 SLICE_X28Y79 SLICE 3 15 xor2 SLICE_X31Y79 SLICE 3 15 xor2 SLICE_X30Y78 SLICE 3 15 xor2 SLICE_X26Y78 SLICE 3 15 xor2 SLICE_X12Y78 SLICE 3 15 xor2 SLICE_X62Y46 SLICE 3 15 xor2 SLICE_X49Y79 SLICE 3 15 xor2 SLICE_X0Y42 SLICE 3 15

Clearly one knows about the LUT's and the other does not. Furthermore, the Floorplanner is showing the outputs coming out of non-existant "xor2" entities. I guess the good news is that the FPGA Editor tells it like it is. (?)

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Martin Euredjian
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Martin Euredjian

That did it. Here's what I defined for XST:

//synthesis attribute LUT_MAP of myXOR2 is YES; module myXOR2 ( output O, input I0, input I1 );

assign O = I0 ^ I1; endmodule

Many thanks!

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Martin Euredjian
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Martin Euredjian

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