Where is Command Reg and Status Reg as mentioned in PCI system architecture (Mindshare) in generated pci32 core?

Hi,

I realize that in cfg.vhd files generated by PCI32 LogiCore does not have command register and status register. From Mindshare book, it said it is "always mandatory" to supply this information. Does anyone know what do I need to do/add?

Cheers!

Reply to
Ace
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I don't believe you have to add anything; they are automatically there.

If you look at the "signal description" section of the "implementation" PDF you will see a description of the command register bits made available to the user interface. This confirms that the register exists...

You do need to use a configuration cycle to write to the command register to enable memory or I/O transfers when initialising the core; see "stimulus.vhd" in the ping_tb testbench for example.

- Brian

Reply to
Brian Drummond

Thank you Brian for clearing that bit for me.

I didn't know that I have to initialise the core. Maybe that's the reason why I still couldn't get the Device and Vendor ID after synthesizing the core on my development board. Can anyone explain when and how is the "configuration cycle" need to be done for the initialising process?

Thank you in advance.

Reply to
Ace

Read the testbench example I suggested.

But this doesn't explain why you can't get the Device/Vendor ID, because you read these through configuration cycles.

When you can read these IDs, you can then use more configuration cycles to initialise the core. This means writing addresses to your Base Address Registers, and permission to perform memory or I/O cycles to the Command/Status register. Only after that, can you perform real memory or I/O transfers to the device.

But if you can't read the Device/Vendor IDs, you have another problem. Did you read the Device/Vendor IDs in simulation? If not, get that working first.

- Brian

Reply to
Brian Drummond

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