Hi FPGA experts
I am a little bit desperate. We have designed a hardware module in EDK
6.2 which was working properly on our ML300 Board. We tested the logical bahaviour with thousands of testcases, and on the Board we executed 8000 instruction. In the end it output the correct result. Now we switched to EDK 7.1 and guess what happend... the module doesnt work anymore. The exact same core already outputs the false result in the first execution of a digit-multiplier. Its really strange as here 25 iterations are required to return the result. Finally exactly 1!!!! bit is incorrect. I have no clue what the problem could be. Is there a possibility that the mapping process somehow failed? Or that the board is broken? Any other ideas what could cause this problems?Cheers for any helpful comment Philipp