What wrong with the DCM of Virtex4 in my project?

I have built a EDK project to program an opb_pci bridge into a virtex4fx60 FPGA, in this design, a 100MHz clock from a crystal was the input for DCM, and a 2x ouput(200Mhz) was for the IDELAYCTRL primitives.

But the opb_bridge didn't work at all. I used a Agilent's oscilloscope to see if the clocks work well or not. The result was that 100Mhz input clock was OK, but the 200Mhz output was a bad one, just like a mass of noise.

So can anyone kindly help me find out what is wrong with the DCM=A3=BF Thank all.

Reply to
Perry
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Howdy Perry,

Unfortunately your description doesn't really provide enough info for people need to help you. You said that you looked at some signals with a scope, but you didn't describe what you saw in detail. Solving problems like this is ALL about detail:

1=2E What voltage swing (and offset from ground) did you see? 2=2E Is your .ucf file correct (pin numbers and voltage type set correctly for both input and outputs signals?) 3=2E Exactly how do you have signals connected in the design (posting the HDL for your clock tree is the best way to have that checked)

Good luck,

Marc

Reply to
Marc Randolph

As I see from the scope, the voltages are not very stable. The voltage swing is range from about 800mv to 1.2v, However, I am not sure if I have got the correct answer to this question, for I am not familiar with using oscilloscopes at present.

yes, i have checked that.

Here is the instance of DCM, copied from the .mhs file of the EDK project: The input frequency is 100MHz, and clk_200mhz_s is the problematic output clock.

BEGIN dcm_module PARAMETER INSTANCE =3D dcm_0 PARAMETER HW_VER =3D 1.00.c PARAMETER C_CLK0_BUF =3D TRUE PARAMETER C_CLK2X_BUF =3D TRUE PARAMETER C_CLKDV_BUF =3D TRUE PARAMETER C_CLKDV_DIVIDE =3D 2.0 PARAMETER C_CLKFX_BUF =3D TRUE PARAMETER C_CLKFX_DIVIDE =3D 1 PARAMETER C_CLKFX_MULTIPLY =3D 3 PARAMETER C_CLKIN_PERIOD =3D 10.000000 PARAMETER C_CLK_FEEDBACK =3D 1X PARAMETER C_DFS_FREQUENCY_MODE =3D HIGH PARAMETER C_DLL_FREQUENCY_MODE =3D LOW PARAMETER C_EXT_RESET_HIGH =3D 1 PORT CLKIN =3D dcm_clk_s PORT CLK0 =3D sys_clk_s PORT CLK2X =3D clk_200mhz_s PORT CLKFB =3D sys_clk_s PORT RST =3D net_gnd PORT LOCKED =3D dcm_0_lock PORT CLKFX =3D proc_clk_s PORT CLKDV =3D dcm_0_CLKDV END

Thanks again for your kindly concern :-)

Reply to
Perry

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