what wrong of this counter ?

I found this was clock source issue, the PLL for mmu clock (on the FPGA board) would appeared clock glitch in low frequency (12 MHz~ 30MHz) . As I used a simple crcuit for verifying as below, ############################################# always @(negedge rst_n or posedge clk_in) if ( !rst_n ) begin toggle_signal

There is a "dirty trick" that allows you to live with a glitch on the falling clock edge, when you really want to trigger only on the rising clock edge: Take the clock input, invert it, and use it then as Count Enable on your counter. That disbles the counter while the clock is High, plus a little bit beyond, and thus masks the double transition of the falling clock edge. You may have to add some delay to the Count Enable input.

This is a BandAid, the proper solution is to terminate the clock line, so that you do not get the glitch. Peter Alfke, Xilinx Applictions. Occasionally also helping an Altera user in distress...

Hi, Peter, Thank for your suggestion. But I have two questions now: (1) if i want to "filter" the clock source for generating a new clear clock, how can i do ? (2) you mentioned "add some delay to ...", can i add use LCELL() delay cell ? And if i use DC synthesis, how can i do and how can i guarantee delay is proper ? thanks

I offered a "BandAid", not a cure. Just invert the clock and use this inverted clock as CE. This does not eliminate the glitch, but it makes sure that the counter does not react to it. Maybe you do not need any extra delay... Peter Alfke