I suppose these will be announced quite soon once the Virtex5 manuals become accessible to mortals ... I was intrigued to see in the Proceedings of ISSCC a design for an incredibly fast 64-bit adder in
90nm CMOS, which might in some way be an answer to the complaints about the carry chains in V4 being too slow for practical use.Abstract: A 64b adder with a single-execution cycle time of 250ps is fabricated in a 90nm CMOS technology. The adder is designed using an energy-delay optimization framework that can rapidly optimize different microarchitectures in the energy-delay space. The microarchitecture with the lowest delay, a sparse radix-4 Ling parallel prefix tree, is chosen. The carry tree uses footless domino logic to minimize delay while the non-critical paths use minimum-size static logic to reduce energy. The adder consumes 311mW from a 1V supply.
Though it used 311mW for a single adder, which would make it impractical to have more than a few per chip; I suspect from the abstract that it was more an advert for a Xilinx optimisation framework than for the actual component that was optimised.
So, what do people want to see? My inner supercomputer designer wants double-precision FPUs, but I suspect they'd be hopelessly interconnect limited; the same almost certainly applies to highly-multiport RAMs suitable for register files, which I'm mentioning because they can be implemented much more cleverly at the ASIC than at the LUT level (long buses with circuits sized to detect small impulses, rather than having to work in the digital realm everywhere).
Tom