Hi, I have a design (basically a FIR filter) that is clocked by the output of a DCM. I understand that I should not do anything before the locked signal goes high. However, what is the right way to do this?
I also have a small state machine that resets the FIR filter, sets some stuff, and then enable everything. The state machine is also clocked by the output of the DCM (it is the only clock of the design). Should I use the locked signal as an asynchronous reset of the state machine so that nothing happens before locked goes high? I wonder if this is what people do, or if there is an easier way. Thanks, David