What to consider for source synchronous clocking?

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Hi everyone, pardon me but I'm pretty new to this.

I'm using a Spartan 3 right now, and I'm trying to provide source
synchronous clock clocking to a SDR SDRAM using DDR register.
The component looks something like this:

OFDDRCPE sdram0OutputClock (
    .PRE(1'b0) );

The input clock is sdram_clk and the output clock to the sdram is
The problem is I'm not sure whether I need to specify any extra
constraints in the UCF file for sdram0_clk.
Is there anything else to take note of?
Are sdram_clk and sdram0_clk considered as different clock domains? If
so how do I get the data back to the sdram_clk domain?

Thanks in advance,

Re: What to consider for source synchronous clocking?
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Once you've assigned the I/O standard of the pin, there's not
much else you can do with constraints.  The clock to the DDR
flip-flop should be on a global net, and there is nothing that
the tools can do to change the clock to output timing.  However
adding a timing constraint for clock to output will cause the
actual timing to be reported in the post p&r static timing report,
which is useful.

Also I noticed you're using clock and ~clock rather than the
clock and 180 degree phase-shifted clock.  Remember that for
DDR the duty cycle is very important so make sure your clock
is duty-cycle corrected in a DCM.


Re: What to consider for source synchronous clocking?
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I'm not sure if it's possible in your design, but by far the simplest
solution would be to use a single external clock that drives both the SDRAM
and all your FPGA logic (through a clock buffer if necessary). If you must
derive the SDRAM clock from the FPGA then one thing you can do is drive out
the derived clock from an I/O and feed it to both the SDRAM and loopback to
an FPGA clock pin (again using a buffer if needed). Both of these approaches
avoid having to worry about IOB delays in the clock output.

Re: What to consider for source synchronous clocking?
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I missed the "SDR" bit when I replied earlier.  I agree that a radial
clock distribution is easiest for single-data-rate parts.  Also forget
the bit about duty cycle, these aren't as picky as DDR parts, which
both edges.

I've made source-synchronous SDR SDRAM systems using a global clock
pin as an I/O (not available in all FPGA series) and pin feedback for
the internal clock.  Otherwise you may need to use a wire for
I wouldn't worry about length matching, especially if your part has
DCM's for phase-shifting the internal clock (and Spartan 3 does).  But
this means that the clock you supply to the DDR output flop is not
the same one used internally for the rest of your logic.

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