Hi, There are several modules in a design, which will be assigned to several member in the group. If the system clock is 100MHz, what timing constraint value should be for each input Pad-to-Setup and Clock-to-Out paths? If clock rate is 200MHz or 300MHz, what about the constraints? I doubt it should be proportional to the clock rates. Thanks a lot.
Knowing nothing else, I would set reg to reg Fmax to the system clock frequency and the pin Tsu and Th to half the system clock period.
-- Mike Treseler
To figure out the setup time requirement for a particular input signal, you have to know what the specs are for the external device is driving that input signal and a few things about the printed circuit board design. One also needs to know just how your design and the external devices are communicating (i.e. global clock, source synchronous, serdes, etc.)
Assuming a global clock, clocking the external device and your design, then the setup time requirement for an input should be set to Tsu(max) = Tcp(min) - Tco(max) - Tskew(max) - Tpcb(max)
where Tcp = clock period of the clock that is driving the input signal. Tco = Clock to output delay of the device that is driving the intput signal. Tskew = Clock skew between the two devices. Tpcb = Propogation delay of the signal on the printed circuit board.
Repeat the above for each and every input.
Tskew and Tpcb are both very dependent on the printed circuit board design. Given your relatively high (for external signals) clock rate, you'll need to pay very close attention to how the clocks and signals all get routed. Signal degradation caused by reflections and stubs and such will not have time to settle out before the next clock edge occurs.
To figure out the clock to output requirement (again for a global clock arrangement) you do essentially the same thing, but now you need to consider the setup time requirement of the external device
Tco(max) = Tcp(min) - Tsu(max) - Tskew(max) - Tpcb(max)
Both of these are assuming that the external devices and your design are both operating off of the same edge of the clock and that whatever is generating the clock signal is generating a clean, fast edge.
If you're really communicating at 100+ MHz, you might want to consider source synchronous clocking instead where there is no 'global' clock, instead each interface generates and sends a clock signal along with the data.
As you can see from both equations, the clock period does enter into figuring out the requirements since it defines the upper bound that you keep whittling things away from in order to determine the design requirement. It also depends on the specs for the external devices that you're talking to, the signaling method and the printed circuit board design requirements.
Kevin Jennings
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