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What's the name of this circuit?

Hi, I need to design a sub-module with 128-bit input and output stream interfaces (4 DWORDs/cycle) which can split the stream at arbitrary DWORD boundaries.

Example input:

DW3 DW2 DW1 DW0 DW7 DW6 DW5 DW4 DWB DWA DW9 DW8

Example output (stream was split after DW4 and re-starts with a full 128-bit word):

DW3 DW2 DW1 DW0

- - - DW4 DW8 DW7 DW6 DW5

- DWB DWA DW9

Before I implement something naively in VHDL, I was wondering how this kind of circuit is called and whether there are any standard architectures for it. The application is, by the way, PCIe TLP splitting and header insertion.

Thanks, Guy.

Reply to
Guy Eschemann
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It is what you put in the data path of a processor that doesn't require data to be aligned. To me, it is related to a barrel shifter, though others might call itsomething else.

-- glen

Reply to
glen herrmannsfeldt

Seems to me to be a FIFO welded to a barrel shifter - buffer the incoming data, pick somewhere between 0 and 4 words, shift them into place. It's slightly different from a normal barrel shifter - words can only go 'downstream', and one of the inputs is 'padding', but that's basically what it is - a big pile of muxes.

I doubt you'll find an off-the-shelf component: it'll probably be less work to implement it yourself.

Theo

Reply to
Theo Markettos

Not really a FIFO, just a pipeline stage so you can concatenate two successive 128-bit input words and then use a variable part-select on that (you could code the part-select operation as a barrel-shift followed by a fixed part-select).

--
Gabor
Reply to
GaborSzakacs

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