What next next big thing coming for HDL?

Hello, I''ve been talking with a co-worker about the HDL languages that are availabile these days, such as VHDL, Verilog, SystemVerilog, and AHDL. In our shop we've used AHDL because it was easy to learn and use and because we've decided to stay with Altera chips. My co-worker believes that in the future these languages will be passed over my better HDL's and that sparked my curiousity. What is the next big HDL that will catch on and grab people from these different HDL backgrounds? Will VHDL, Verilog, AHLD, or SystemVerilog be replaced by something better? If so, what do you think it will be?

thanks, joe

Reply to
jjlindula
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While far from the "next big thing", I'm getting ready to convert a spreadsheet into an FPGA programming language. I'm just getting started with FPGAs and I find I can't get my C-like view of algorithms into Verilog (but, again, I just getting started and don't really know Verilog).

The idea is to use the cells as registers and have the "next state" be a function of the other registers (err, cells) in the spreadsheet.

I've modified the open-source spreadsheet, sc, so that each cell has two values, the current value and the next value. To simulate a clock I calculate the next value for each cell in the sheet, then go through it again copying the next value to the current value. I need to add two new functions, one to read a value into a cell from a file, and another to write a value.

I should be able to save/convert the spreadsheet as either a C program or as RTL Verilog. I figure the spreadsheet will be slow but easy to debug, the C will be faster (but not as fast as a hand coded C program), and the Verilog will be fastest if it makes it into an FPGA.

I think the conversion from spreadsheet to Verilog will be mechanical, so the big question is whether or not a spreadsheet is a useful tool for expressing algorithms.

Suggestions, criticisms, and best of all "it's been done" are all appreciated.

Bob

Reply to
Bob Smith

Hello,

snipped-for-privacy@hotmail.com schrieb:

Maybe SystemC for it's ability do to software/hardware co-design?

Regards,

Norbert

Reply to
Norbert Stuhrmann

Hello, I've been doing some web researching on the next HDL and I've found interest in SystemVerilog, SystemC and EVHDL, and Confluence. In my shop we use Altera's AHLD language which is easy to learn and work in. A co-worker and I believe that AHDL will eventually die and maybe VHDL or Verilog too. But what will replace these HDL's is a good discussion topic. I wished there was something out their that was as easy as Altera's AHDL.

joe

Norbert Stuhrmann wrote:

Reply to
jjlindula

Reply to
ChampDog
10 years from now, I will say SystemVerilog. 20 years from now, I will say Microsoft will get involved in our world. Something like a .NET framework will be introduced for all the launguages (SW and HDL). With the framework, you can choose whatever languages as you like even if software language (e.g. Java, C#, C++, VB and etc.). Having say that, 30 years from now, we no l> Hello, I''ve been talking with a co-worker about the HDL languages that
Reply to
ChampDog

Not anymore, Bluespec and Celoxica both offer SystemC synthesis products. There is also a SystemC Synthesizable subset (still in draft?)

Hans

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Reply to
Hans

I would be interested why you found interest in the listed ones and not in MyHDL or JHDL?

I don't want to argue about SymstemC and SystemVerilog, but why e.g. Confluence, which from my feeling is getting less and less users?

Cheers,

Guenter

Reply to
Guenter

Guenter,

Hello, I'm glad you mentioned those two examples. I wasn't aware of them and didn't come across them in the web seaching I did. I will certainly look them over. What's your opinion of these two HDL's, are they catching on with people and are they easy to use? A lot of the newer HDL's are very high level languages which tend to look very familiar to C. For me that takes a little getting used to, I'm still thinking at the gate level, but I can diffently see the advantage with these HDL's.

Thanks and keep the opinions coming.

joe

Guenter wrote:

Reply to
jjlindula

OK, I thought you had already ruled them out. There is actually another one, I think it is called perl HDL.

At the end I think they are used by people that know the respective language. I am not very familiar with JHDL. I like to use MyHDL, because on the verification side it provides all the nice things that Python provides. Especially in DSP applications there are rich Python modules that I can use to generate reference models or stimulus for the simulation and in connection with the unittest modul do a self checking test bench based on assertions.

On the other side it is also possible to model hardware in MyHDL and convert it into synthesizable Verilog (at the moment VHDL is in production).

At the end, it comes down to the designer's preference and a path to be able to finish the job. At the end of that path there are always the vendor tools. So looking at them will show you which way to go.

Consider how much in the past people tooted the dead of one or the other major HDL's like Verilog or VHDL. Both are still around and you see vendors adding new features of them to their tools.

Reply to
Guenter

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